Features
DATASHEET
RX630 Group
Renesas MCUs
R01DS0060EJ0160
Rev.1.60
May 19, 2014
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,
up to 2-MB flash memory, USB 2.0 full-speed function interface,
CAN, 10- & 12-bit A/D converter, RTC, up to 22 comms interfaces
Features
■
32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU
clock cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
Two types of debugging interfaces: JTAG and FINE (two-line)
PLQP0176KB-A
PLQP0144KA-A
PLQP0100KB-A
PLQP0080KB-A
24 × 24 mm, 0.5-mm pitch
20 × 20 mm, 0.5-mm pitch
14 × 14 mm, 0.5-mm pitch
12 × 12 mm, 0.5-mm pitch
PTLG0177JB-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100KA-A 5.5 × 5.5 mm, 0.5-mm pitch
■
Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral
functions draws only 500
μA/MHz.
RTC is capable of operation from a dedicated power supply (min.
operating voltage: 2.3 V).
Four low-power modes
PLBG0176GA-A 13 × 13 mm, 0.8-mm pitch
■
Up to 22 communications interfaces
USB 2.0 full-speed function interface (1 channel)
CAN (compliant with ISO11898-1), incorporating 32 mailboxes
(up to 3 channels)
SCI with multiple functionalities (up to 13 channels)
Choose from among asynchronous mode, clock-synchronous
mode, smart-card interface mode, simple SPI, simple I
2
C, and
extended serial mode.
I
2
C bus interface for transfer at up to 1 Mbps (up to 4 channels)
RSPI for high-speed transfer (up to 3 channels)
■
On-chip main flash memory, no wait states
100-MHz operation, 10-ns read cycle (no wait states)
384-Kbyte to 2-Mbyte capacities
User code is programmable by on-board or off-board
programming.
■
On-chip data flash memory
Max. 32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
■
External address space
8 CS areas (8 × 16 Mbytes)
Multiplexed address data or separate address lines are selectable
per area.
8-, 16-, or 32-bit bus space is selectable per area
■
On-chip SRAM, no wait states
32- to 128-Kbyte capacities
For instructions and operands
Can provide backup on deep software standby
■
Up to 20 extended-function timers
16-bit MTU2: input capture, output capture, complementary PWM
output, phase-counting mode (6 channels)
16-bit TPU: input capture, output capture, phase-counting mode
(12 channels)
8-bit TMR (4 channels)
16-bit compare-match timers (4 channels)
■
DMA
DMAC: Incorporates four channels
DTC
■
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■
A/D converter for 1-MHz operation
Up to 21 12-bit channels, and incorporating 1 sample-and-hold
circuit
Up to 8 10-bit channels, and incorporating 1 sample-and-hold
circuit
Addition of results of A/D conversion (in the 12-bit A/D converter)
self-diagnosis (for the 10-bit A/D converter)
■
Clock functions
External crystal oscillator or internal PLL for operation at 4 to 16
MHz
Internal 125-kHz LOCO and 50-MHz HOCO
125-kHz clock for the IWDT
Frequency of the oscillator for sub-clock generation: 32 kHz
■
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Time capture function
(for capturing times in response to event-signal input on external
pins)
■
Independent watchdog timer
125-kHz LOCO clock operation
■
10-bit D/A converter: 2 channels
■
Temperature sensor for measuring temperature
within the chip
■
Register write protection function can protect
values in important registers against overwriting.
■
Up to 148 general I/O port pins for GPIO
5-V tolerance, open drain, input pull-up, switchable driving ability
■
Useful functions for IEC60730 compliance
Oscillation-stop detection, frequency measurement, CRC, IWDT,
self-diagnostic function for the A/D converter, etc.
■
Unique ID
16-byte ID code is provided for each chip (only for the G version)
■
Operating temp. range
D version: -40 to +85°C
G version: -40 to +105°C
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 1 of 154
RX630 Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1
lists the specifications in outline, and
Table 1.2
lists the functions of products.
Table 1.1
shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package and the ROM capacity. For details, see
Table 1.2, Comparison of
Functions for Different Packages.
Table 1.1
Classification
CPU
Outline of Specifications (1/5)
Module/Function
CPU
Description
Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system
clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point operation instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32
64 bits
On-chip divider: 32 / 32
32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
Single precision floating point (32 bits)
Data types and floating-point exceptions in conformance with the IEEE754 standard
Capacity: 384 Kbytes, 512 Kbytes, 768 Kbytes, 1 Mbyte, 1.5 Mbytes, 2 Mbytes
100 MHz, no-wait access
On-board programming: Four types
Off-board programming (parallel programmer mode)
FPU
Memory
ROM
RAM
E
2
data flash
MCU operating modes
Clock
Clock generation circuit
Capacity: 64 Kbytes, 96 Kbytes, 128 Kbytes
100 MHz, no-wait access
Capacity: 32 Kbytes
Programming/erasing: 100,000 times
Single-chip mode, on-chip ROM enabled extended mode, and on-chip ROM disabled
extended mode (software switching)
Main clock oscillator, sub-clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and dedicated on-chip oscillator for the IWDT
Main-clock oscillation stop detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), FlashIF clock (FCLK) and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLK):
Up to 50 MHz
Flash IF run in synchronization with the FlashIF clock (FCLK): Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): Up to 50 MHz
RES# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer
reset, watchdog timer reset, deep software standby reset, and software reset
When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
Reset
Voltage detection circuit
R01DS0060EJ0160 Rev.1.60
May 19, 2014
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RX630 Group
Table 1.1
Classification
Low power
consumption
1. Overview
Outline of Specifications (2/5)
Module/Function
Low power
consumption facilities
Description
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Battery backup function
Peripheral function interrupts: 180 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: One source
Non-maskable interrupts: 6 sources
Sixteen levels specifiable for the order of priority
Interrupt
Interrupt controller
(ICUb)
External bus extension
The external address space can be divided into eight areas (CS0 to CS7), each with
independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7)
A chip-select signal (CS0# to CS7#) can be output for each area.
Each area is specifiable as an 8-, 16- or 32-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: External interrupts and interrupt requests from peripheral functions
177-pin TFLGA (in planning), 176-pin LFBGA (in planning), 176-pin LQFP
I/O pins: 148
Input pin: 1
Pull-up resistors: 148
Open-drain outputs: 148
5-V tolerance: 54
145-pin TFLGA (in planning), 144-pin LQFP
I/O pins: 117
Input pin: 1
Pull-up resistors: 117
Open-drain outputs: 117
5-V tolerance: 53
100-pin TFLGA (in planning), 100-pin LQFP
I/O pins: 78
Input pin: 1
Pull-up resistors: 78
Open-drain outputs: 78
5-V tolerance: 44
80-pin LQFP (in planning)
I/O pins: 58
Input pin: 1
Pull-up resistors: 58
Open-drain outputs: 58
5-V tolerance: 34
DMA
DMA controller
(DMACA)
Data transfer controller
(DTCa)
I/O ports
General I/O port pins
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 3 of 154
RX630 Group
Table 1.1
Classification
Timers
1. Overview
Outline of Specifications (3/5)
Module/Function
16-bit timer pulse unit
(TPUa)
Description
Multi-function timer
pulse unit 2 (MTU2a)
(16 bits × 6 channels) × 2 units
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Supports the input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Signals from the input capture pins are input via a digital filter
Clock frequency measuring method
(16 bits × 6 channels) × 1 unit
Time bases for the 6 16-bit timer channels can be provided via up to 16 pulse-input/
output lines and three pulse-input lines
Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/
4, PCLK/16, PCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5,
for which only four signals are available.
Input capture function
21 output compare/input capture registers
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Digital filter
Signals from the input capture pins are input via a digital filter
PPG output trigger can be generated
Clock frequency measuring function
The MTU or unit 0 TPU module can be used to monitor the main clock, sub-clock, HOCO
clock, LOCO clock, and PLL clock for abnormal frequencies.
Controls the high-impedance state of the MTU’s waveform output pins
(4 bits × 4 groups) × 2 units
Pulse output with the MTU or TPU output as a trigger
Maximum of 32 pulse-output possible
(8 bits × 2 channels) × 2 units
Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
(16 bits × 2 channels) × 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/
512)
Clock sources: Main clock, sub-clock
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Battery backup operation
Time-capture facility for three values
14 bits × 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
14 bits × 1 channel
Counter-input clock: Dedicated on-chip oscillator for the IWDT
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
Frequency
measurement function
(MCK)
Port output enable 2
(POE2a)
Programmable pulse
generator (PPG)
8-bit timers (TMR)
Compare match timer
(CMT)
Realtime clock (RTCa)
Watchdog timer
(WDTA)
Independent watchdog
timer (IWDTA)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 4 of 154
RX630 Group
Table 1.1
Classification
Communication
function
1. Overview
Outline of Specifications (4/5)
Module/Function
USB 2.0 function
module (USBa)
Description
Includes a UDC (USB Device Controller) and transceiver for USB 2.0
Single port
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps)
Self-power mode and bus power are selectable
Incorporates 2 Kbytes of RAM as a transfer buffer
Serial communications
interfaces (SCIc, SCId)
13 channels (SCIc: 12 channels + SCId: 1 channel)
SCIc
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Simple I
2
C
Simple SPI
SCId (The following functions are added to SCIc)
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
4 channels (one of them is FM+)
Communication formats
I
2
C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 1 Mbps (channel 0)
1 channel
Supports protocol control for the IEBus
Half-duplex asynchronous transfer
Multi-master operation
Broadcast communications function
Two selectable modes, differentiated by transfer rate
3 channels
Compliance with the ISO11898-1 specification (standard frame and extended frame)
32 mailboxes per channel
3 channels
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
1 unit (1 unit × 21 channels)
12-bit resolution
Conversion time: 1.0
s
per channel (in operation with PCLK at 50 MHz)
Operating mode
Scan mode (single scan mode or continuous scan mode)
Sample-and-hold function
Reference voltage generation
Three ways to start A/D conversion
Conversion can be started by a software trigger, a trigger from a timer (MTU, TPU, or
TMR), or an external trigger signal
A/D conversion of the temperature sensor output
I
2
C bus interfaces
(RIIC)
IEBus (IEB)
CAN module (CAN)
Serial peripheral
interfaces (RSPI)
12-bit A/D converter (S12ADa)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
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