PRELIMINARY
PFM21030
SPECIFICATION
2110-2170 MHz, 30W, 2-Stage Power Module
Enhancement-Mode Lateral MOSFETs
This versatile UMTS module provides excellent linearity and efficiency in
Package Type: Surface Mount
a low-cost surface mount package. The PFM21030 includes two stages
PN: PFM21030SM
of amplification, along with internal sense FETs that are on the same
silicon die as the RF devices. These thermally coupled sense FETs
simplify the task of bias temperature compensation of the overall amplifier.
The module includes RF input, interstage, and output matching elements.
The source and load impedances required for optimum operation of the
module are much higher (and simpler to realize) than for unmatched Si
LDMOS transistors of similar performance.
The surface mount package base is typically soldered to a conventional
PCB pad with an array of via holes for grounding and thermal sinking
of the module. Optimized internal construction supports low FET
channel temperature for reliable operation.
Package Type: Flange
PN: PFM21030F
•
27 dB Gain
•
30 Watts Peak Output Power
•
Internal Tracking FETs
(for improved bias control)
•
WCDMA Performance
5 Watts Average Output Level
18% Power Added Efficiency
–45 dBc ACPR
Module Schematic Diagram
Module Substrate
Q1 Die Carrier
Gate 1
RF IN
Q1
Lead
Input
Match
Output
Match
Input
Match
Q2 Die Carrier
Q2
Output
Match
Drain 2
RF OUT
Lead
S1
S2
Sense S1
Gate 2
Sense S2
Lead
Lead
Lead
D1
Lead
Note: Additionally, there are 250K Ohm resistors connected in shunt with all leads, to enhance ESD protection.
Page 1 of 13
Specifications subject to change without notice. US Patent No.6,822,321
http://www.cree.com/
Rev. 3
PFM21030
Electrical Specification
Parameter
Min
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Operating Frequency
Gain
Gain Compression at
Pout =30 Watts
Gain Flatness over any
30 MHz bandwidth
Deviation from Linear
Phase over any 30
MHz bandwidth
Group Delay
ACPR with WCDMA
Pave = 5 W
Efficiency under
WCDMA Protocol,
Pave = 5 W
Efficiency @ 30W
CW Output
DC Drain Supply
Voltage
Operating
Temperature Range
(base temperature)
Gain Variation versus
Temperature
Output Mismatch
Stress
Stability
Theta jc (channel)
Quiescent Currents
a) Q1
b) Q2
Tracking FET
Periphery Ratio
a) Stg 1 Track
b) Stg 2 Track
ESD Protection
a) Human Body Model
b) Machine Model
2110
25
-
-
-
-
-40
17
Limits
Typ
-
26.7
1.3
±
0.1
±
1.0
3.5
-44
19
40
Units
Max
2170
30
2.0
±
0.3
±
2.0
3.8
-
-
-
30
+115
-
30
-
2.1
MHz
dB
dB
dB
°
nanosec
dBc
%
%
Volts
°C
dB/°C
Watts
CW
dBc
°C/W
mA
mA
%
%
Note 1.
Comments
Pulsed CW compression measurement
(12
µsec
pulse, 120
µsec
period, 10%
duty cycle).
Includes delay of test fixture (~0.6
nanoseconds).
Note 3. Refer to applications data for
performance with other protocols.
Note 3.
24
-40
-
-
-60
-
27
-
-0.033
-
-
-
80
240
3.0
1.7
Testing for conformance with RF
specifications is at +27 V.
Testing for conformance with RF
specification is at +25
°C.
Bias quiescent currents held constant.
VSWR 10:1, all phase angles. No
degradation in output power before &
after test.
0<Pout<44.8 dBm CW, 3:1 VSWR
Theta jc is for output device. Verified
with IR scan. Note 2.
These DC quiescent currents are typical
of the levels that produce optimum
linearity for CDMA protocol.
Ratio of sense FET current, relative to RF
FET current. Ratios are: Stg 1: 33:1;
Stg 2: 58:1 Gates of sense & RF FETs
are DC connected. Measured with no RF
signal present.
a) 2000V, 100 pF, 1500 Ohms
b) 400V, 200 pF, zero Ohms
Mil STD 883E, Method 3015 for Human
Body Model and for Machine Model.
17
18
Class 1
Class M3
Page 2 of 13
Specifications subject to change without notice. U.S. Patent No.6,822,321
http://www.cree.com/
Rev. 2
PFM21030
Electrical Specification (Continued)
MAXIMUM RATINGS
Rating
19
DC Drain Supply
a) Drain-to-Source Voltage, (V
GS
=0), D1 & D2
& Track D1 & Track D2
b) Normal Operation (Class AB operation)
DC Gate Supply
a) Gate-to-source Voltage (V
DS
=0)
Normal Operation (Class AB operation)
RF Input Power
Maximum Power Dissipation (T
≤
+85
°C)
a) Derate above +85
°C
base temperature.
Maximum Channel Operating Temperature
Storage Temperature Range
Symbol
V
DS
V
D_SUPPLY
V
G_SUPPLY
P
IN
P
TOTAL
T
CH
T
STG
V
GS
Value
+50
+30
-0.5<V
GS
<+15
0<V
GS
<+6
+25
65
-0.7
+200
-40 to +150
Units
Volts DC
Volts DC
Volts DC
Volts DC
dBm
Watts
Watts/°C
°C
°C
20
21
22
23
24
RECOMMENDED SOURCE AND LOAD IMPEDANCES
Impedance
Nominal Source
Impedance for
Optimum Operation
Nominal Load
Impedance for
Optimum Operation
18.3 – j0.1
Units
Ohms
Comments
Matched for optimum linearity and gain flatness. Impedance
is looking from the module input lead into the input matching
circuit. Reference plane is 0.105 inches from input end of
module.
Matched for optimum efficiency under WCDMA protocol.
Impedance is from the module output lead looking into the
output matching circuit. Reference plane is 0.105 inches from
output end of module.
23.7 + j3.8
Ohms
Specification Notes:
1) The module is mounted in a test fixture with external matching elements for all testing. Quiescent current bias
conditions are those appropriate for minimum ACPR under CDMA protocol. Supply voltage for all tests is
+27 volts DC. Testing is at +25
°C
unless otherwise specified.
2) Theta jc is measured with a package mounting (base) temp of +85
°C,
and with 10 Watts CW output.
3) Pout=5 Watts average; WCDMA protocol:
(3GPP Test Model 1, 64 DPCH.)
.
ACPR conditions: 5.00 MHz offset, 3.84 MHz BW (crest factor = 11 dB).
4) Sense FETs are scaled versions of the main RF FETs, formed from electrically isolated cells at end of the RF
structure. Current scales according to periphery (threshold voltages offset is less than
±150
millivolts between
adjacent devices). RF & Sense FET gates and sources are DC connected. Drains are DC isolated. Leads S1 & S2
are DC connected to drains of sense FETs 1 & 2. Sources are connected to package base. Sense FETs are
electrically isolated from the RF signals.
Page 3 of 13
Specifications subject to change without notice. U.S. Patent No.6,822,321
http://www.cree.com/
Rev. 2
PFM21030
Typical Module Performance
T=+25
°C,
unless otherwise noted. Data is for module in a test fixture with external matching elements. See following
page for test fixture details.
Typical Small-Signal Gain vs. Frequency
28
Typical CW 2-Tone Intermods vs. Output Power
-10
IM3L
IM3U
IM5L
IM5U
IM7L
-40
-50
-60
-70
27
29
31
33
35
37
39
41
43
IM7U
Intermod Rejection (dBc)
2050
2110
2170
2230
2290
2350
27
-20
-30
Gain (dB)
26
25
24
23
1990
Frequency (MHz)
Average Output Power (dBm)
Typical Input & Output Return Loss vs Freq.
0
Typical Gain & Efficiency vs CW Output Power
28
27
GAIN
45
40
-2
-4
Return Loss (dB)
-6
Gain (dB)
OUTPUT
25
24
23
EFFICIENCY
30
25
20
15
10
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
-8
-1 0
INPUT
-1 2
22
-1 4
21
-1 6
2 0 5 0
2 0 8 0
2 1 1 0
2 1 4 0
2 1 7 0
2 2 0 0
2 2 3 0
Output Power (dBm)
Frequency (MHz)
Note: The above data is for initial prototype units. Consult the factory for latest data.
Page 4 of 13
Specifications subject to change without notice. U.S. Patent No.6,822,321
http://www.cree.com/
Rev. 2
Efficiency (%)
26
35
PFM21030
PFM21030SM Package Outline
PFM21030F Package Outline
Page 5 of 13
Specifications subject to change without notice. U.S. Patent No.6,822,321
http://www.cree.com/
Rev. 2
51mcu
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