CS5150
CPU 4−Bit Synchronous
Buck Controller
The CS5150 is a 4−bit synchronous dual N−Channel buck
controller. It is designed to provide unprecedented transient response
for today’s demanding high−density, high−speed logic. The regulator
operates using a proprietary control method, which allows a 100 ns
response time to load transients. The CS5150 is designed to operate
over a 4.25−16 V range (V
CC
) using 12 V to power the IC and 5.0 V or
12 V as the main supply for conversion.
The CS5150 is specifically designed to power Pentium® Pro
processors and other high performance core logic. It includes the
following features: on board, 4−bit DAC, short circuit protection,
1.0% output tolerance, V
CC
monitor, and programmable Soft Start
capability. The CS5150 is upward compatible with the 5−bit
CS5155H, allowing the mother board designer the capability of using
either the CS5150 or the CS5155 with no change in layout. The
CS5150 is available in 16 pin surface mount.
Features
•
Dual N−Channel Design
•
Excess of 1.0 MHz Operation
•
100 ns Transient Response
•
4−Bit DAC
•
Upward Compatible with 5−Bit CS5155/CS5156
•
30 ns Gate Rise/Fall Times
•
1.0% DAC Accuracy
•
5.0 V & 12 V Operation
•
Remote Sense
•
Programmable Soft Start
•
Lossless Short Circuit Protection
•
V
CC
Monitor
•
25 ns FET Nonoverlap Time
•
Adaptive Voltage Positioning
•
V
2
™
Control Topology
•
Current Sharing
•
Overvoltage Protection
16
1
DIP−16
N SUFFIX
CASE 648
A
WL, L
YY, Y
WW, W
1
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MARKING
DIAGRAMS
16
16
CS5150
AWLYWW
1
1
SOIC−16
D SUFFIX
CASE 751B
16
CS5150
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
V
ID0
V
ID1
V
ID2
V
ID3
SS
NC
C
OFF
V
FFB
1
V
FB
COMP
LGND
V
CC1
V
GATE(L)
PGND
V
GATE(H)
V
CC2
ORDERING INFORMATION
Device
CS5150GD16
CS5150GDR16
CS5150GN16
Package
SO−16
SO−16
DIP−16
Shipping
48 Units/Rail
2500 Tape & Reel
25 Units/Rail
©
Semiconductor Components Industries, LLC, 2006
July, 2006
−
Rev. 5
1
Publication Order Number:
CS5150/D
CS5150
12 V
5.0 V
0.1
μF
V
CC1
V
ID0
V
ID1
V
ID2
V
ID3
V
ID0
V
ID1
V
ID2
V
ID3
C
OFF
330 pF
SS
0.1
μF
COMP
LGND
IRL3103
V
GATE(L)
PGND
V
CC2
IRL3103
2.0
μH
1200
μF/16
V
×
3
AIEI
V
GATE(H)
2.1 V to 3.5 V @ 13 A
CS5150
V
FB
3.3 k
V
FFB
100 pF
0.33
μF
1200
μF/16
V
×
5
AIEI
Figure 1. Application Diagram, Switching Power Supply for Core Logic
−
Pentium
)
Pro Processor
ABSOLUTE MAXIMUM RATINGS*
Rating
Operating Junction Temperature, T
J
Lead Temperature Soldering:
Storage Temperature Range, T
S
ESD Susceptibility (Human Body Model)
1. 10 second maximum.
2. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Wave Solder (through hole styles only) (Note 1)
Reflow: (SMD styles only) (Note 2)
Value
0 to 150
260 peak
230 peak
−65
to +150
2.0
Unit
°C
°C
°C
kV
ABSOLUTE MAXIMUM RATINGS
Pin Name
V
CC1
V
CC2
SS
COMP
V
FB
C
OFF
V
FFB
V
ID0
−
V
ID3
V
GATE(H)
V
GATE(L)
LGND
PGND
Max Operating Voltage
16 V/−0.3 V
16 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
6.0 V/−0.3 V
16 V/−0.3 V
16 V/−0.3 V
0V
0V
Max Current
25 mA DC/1.5 A peak
20 mA DC/1.5 A peak
−100
μA
200
μA
−0.2
μA
−0.2
μA
−0.2
μA
−50
μA
100 mA DC/1.5 A peak
100 mA DC/1.5 A peak
25 mA
100 mA DC/1.5 A peak
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2
CS5150
ELECTRICAL CHARACTERISTICS
(0°C < T
A
< +70°C; 0°C < T
J
< +85°C; 8.0 V < V
CC1
< 14 V; 5.0 V < V
CC2
< 14 V;
DAC Code: V
ID2
= V
ID1
= V
ID0
= 1; V
ID3
= 0
;
CV
GATE(L)
and CV
GATE(H)
= 1.0 nF; C
OFF
= 330 pF; C
SS
= 0.1
μF,
unless otherwise specified.)
Characteristic
Error Amplifier
V
FB
Bias Current
Open Loop Gain
Unity Gain Bandwidth
COMP SINK Current
COMP SOURCE Current
COMP CLAMP Current
COMP High Voltage
COMP Low Voltage
PSRR
V
CC1
Monitor
Start Threshold
Stop Threshold
Hysteresis
DAC
Input Threshold
Input Pull Up Resistance
Pull Up Voltage
Accuracy
V
ID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
V
ID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
V
ID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
V
ID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1.2315
2.1186
2.2176
2.3166
2.4156
2.5146
2.6136
2.7126
2.8116
2.9106
3.0096
3.1086
3.2076
3.3066
3.4056
3.5046
1.2440
2.1400
2.2400
2.3400
2.4400
2.5400
2.6400
2.7400
2.8400
2.9400
3.0400
3.1400
3.2400
3.3400
3.4400
3.5400
1.2564
2.1614
2.2624
2.3634
2.4644
2.5654
2.6664
2.7674
2.8684
2.9694
3.0704
3.1714
3.2724
3.3734
3.4744
3.5754
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ID0,
V
ID1
, V
ID2
, V
ID3
V
ID0,
V
ID1
, V
ID2
, V
ID3
−
Measure V
FB
= COMP, 25°C
≤
T
J
≤
85°C
1.00
25
4.85
−
1.25
50
5.00
−
2.40
100
5.15
1.0
V
kΩ
V
%
Output switching
Output not switching
Start−Stop
3.75
3.70
−
3.90
3.85
50
4.05
4.00
−
V
V
mV
V
FB
= 0 V
1.25 V < V
COMP
< 4.0 V; Note 3
Note 3
V
COMP
= 1.5 V; V
FB
= 3.0 V; V
SS
> 2.0 V
V
COMP
= 1.2 V; V
FB
= 2.7 V; V
SS
= 5.0 V
V
COMP
= 0 V; V
FB
= 2.7 V
V
FB
= 2.7 V; V
SS
= 5.0 V
V
FB
= 3.0 V
8.0 V < V
CC1
< 14 V @ 1.0 kHz; Note 3
−
50
500
0.4
30
0.4
4.0
−
60
0.3
60
3000
2.5
50
1.0
4.3
160
85
1.0
−
−
8.0
70
1.6
5.0
600
−
μA
dB
kHz
mA
μA
mA
V
mV
dB
Test Conditions
Min
Typ
Max
Unit
3. Guaranteed by design, not 100% tested in production.
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3
CS5150
ELECTRICAL CHARACTERISTICS (continued)
(0°C < T
A
< +70°C; 0°C < T
J
< +85°C; 8.0 V < V
CC1
< 14 V;
5.0 V < V
CC2
< 14 V; DAC Code: V
ID2
= V
ID1
= V
ID0
=1; V
ID3
=
0;
CV
GATE(L)
and CV
GATE(H)
= 1.0 nF; C
OFF
= 330 pF; C
SS
= 0.1
μF,
unless
otherwise specified.)
Characteristic
V
GATE(H)
and V
GATE(L)
Out SOURCE Sat at 100 mA
Out SINK Sat at 100 mA
Out Rise Time
Out Fall Time
Shoot−Through Current
Delay V
GATE(H)
to V
GATE(L)
Delay V
GATE(L)
to V
GATE(H)
V
GATE(H),
V
GATE(L)
Resistance
V
GATE(H),
V
GATE(L)
Schottky
Soft Start (SS)
Charge Time
Pulse Period
Duty Cycle
COMP Clamp Voltage
V
FFB
SS Fault Disable
High Threshold
PWM Comparator
Transient Response
V
FFB
Bias Current
Supply Current
I
CC1
I
CC2
Operating I
CC1
Operating I
CC2
C
OFF
Normal Charge Time
Extension Charge Time
Discharge Current
Time Out Timer
Time Out Time
Fault Mode Duty Cycle
V
FB
= V
COMP
; V
FFB
= 2.0 V;
Record V
GATE(H)
Pulse High Duration
V
FFB
= 0V
10
35
30
50
50
65
μs
%
V
FFB
= 1.5 V; V
SS
= 5.0 V
V
SS
= V
FFB
= 0
C
OFF
to 5.0 V; V
FB
> 1.0 V
1.0
5.0
5.0
1.6
8.0
−
2.2
11.0
−
μs
μs
mA
No Switching
No Switching
V
FB
= COMP = V
FFB
V
FB
= COMP = V
FFB
−
−
−
−
8.5
1.6
8.0
2.0
13.5
3.0
13
5.0
mA
mA
mA
mA
V
FFB
= 0 to 5.0 V to V
GATE(H)
= 9.0 V to 1.0 V;
V
CC1
= V
CC2
= 12 V
V
FFB
= 0 V
−
−
100
0.3
125
−
ns
μA
−
−
(Charge Time /Pulse Period)
×
100
V
FB
= 0 V; V
SS
= 0
V
GATE(H)
= Low; V
GATE(L)
= Low
−
1.6
25
1.0
0.50
0.9
−
3.3
100
3.3
0.95
1.0
2.5
5.0
200
6.0
1.10
1.1
3.0
ms
ms
%
V
V
V
Measure V
CC1
−
V
GATE(L)
; V
CC2
−
V
GATE(H)
Measure V
GATE(H)
−
V
PGND
; V
GATE(L)
−
V
PGND
1.0 V < V
GATE(H)
< 9.0 V;
1.0 V < V
GATE(L)
< 9.0 V; V
CC1
= V
CC2
= 12 V
9.0 V > V
GATE(H)
> 1.0 V;
9.0 V > V
GATE(L)
> 1.0 V; V
CC1
= V
CC2
= 12 V
Note 4
V
GATE(H)
falling to 2.0 V
;
V
CC1
= V
CC2
= 8.0 V
V
GATE(L)
rising to 2.0 V
V
GATE(L)
falling to 2.0 V; V
CC1
= V
CC2
= 8.0 V
V
GATE(H)
rising to 2.0 V
Resistor to LGND.
LGND to V
GATE(H)
@ 10 mA;
LGND to V
GATE(L)
@ 10 mA
−
−
−
−
−
−
−
20
−
1.2
1.0
30
30
−
25
25
50
600
2.0
1.5
50
50
50
50
50
100
800
V
V
ns
ns
mA
ns
ns
kΩ
mV
Test Conditions
Min
Typ
Max
Unit
4. Guaranteed by design, not 100% tested in production.
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4
CS5150
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO−16, DIP−16
1, 2, 3, 4
PIN SYMBOL
V
ID0
−V
ID3
FUNCTION
Voltage ID DAC input pins. These pins are internally pulled
up to 5.0 V providing logic ones if left open. The DAC range
is 2.14 V to 3.54 V with 100 mV increments. V
ID0
−
V
ID3
select the desired DAC output voltage. Leaving all 4 DAC
input pins open results in a DAC output voltage of 1.244 V,
allowing for adjustable output voltage, using a traditional
resistor divider.
Soft Start Pin. A capacitor from this pin to LGND in conjunc-
tion with internal 60
μA
current source provides Soft Start
function for the controller. This pin disables fault detect func-
tion during Soft Start. When a fault is detected, the Soft Start
capacitor is slowly discharged by internal 2.0
μA
current
source setting the time out before trying to restart the IC.
Charge/discharge current ratio of 30 sets the duty cycle for
the IC when the regulator output is shorted.
No Connection.
A capacitor from this pin to ground sets the time duration for
the on board one shot, which is used for the constant off time
architecture.
Fast feedback connection to the PWM comparator. This pin
is connected to the regulator output. The inner feedback loop
terminates on time.
Boosted power for the high side gate driver.
High FET driver pin capable of 1.5 A peak switching current.
Internal circuit prevents V
GATE(H)
and V
GATE(L)
from being in
high state simultaneously.
High current ground for the IC. The MOSFET drivers are
referenced to this pin. Input capacitor ground and the source
of lower FET should be tied to this pin.
Low FET driver pin capable of 1.5 A peak switching current.
Input power for the IC and low side gate driver.
Signal ground for the IC. All control circuits are referenced to
this pin.
Error amplifier compensation pin. A capacitor to ground
should be provided externally to compensate the amplifier.
Error amplifier DC feedback input. This is the master voltage
feedback which sets the output voltage. This pin can be con-
nected directly to the output or a remote sense trace.
5
SS
6
7
NC
C
OFF
8
V
FFB
9
10
V
CC2
V
GATE(H)
11
PGND
12
13
14
15
16
V
GATE(L)
V
CC1
LGND
COMP
V
FB
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