• Available in a 119-ball BGA package (CY7C1330AV25
and CY7C1332AV25)
Functional Description
The CY7C1330AV25 and CY7C1332AV25 are high perfor-
mance, Synchronous Pipelined SRAMs designed with late
write operation. These SRAMs can achieve speeds up to 250
MHz. Each memory cell consists of six transistors.
Late write feature avoids an idle cycle required during the
turnaround of the bus from a read to a write.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (K). The synchronous
inputs include all addresses (A), all data inputs (DQ
[a:d]
), Chip
Enable (CE), Byte Write Selects (BWS
[a:d]
), and read-write
control (WE). Read or Write Operations can be initiated with
the chip enable pin (CE). This signal allows the user to
select/deselect the device when desired.
Power down feature is accomplished by pulling the
Synchronous signal ZZ HIGH.
Output Enable (OE) is an asynchronous input signal. OE can
be used to disable the outputs at any given time.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Configuration
CY7C1330AV25 – 512K x 36
CY7C1332AV25 – 1M x 18
Logic Block Diagram
K,K
Clock
Buffer
D Data-In REG.
CE Q (2stage)
OUTOUT
REGISTERS
and LOGIC
A
x
CE
CONTROL
and WRITE
LOGIC
512Kx36
1Mx18
DQ
x
WE
BWS
x
MEMORY
ARRAY
ZZ
OE
A
X
DQ
X
BWS
X
512Kx36
X = 18:0 X = a, b, c, d X = a, b, c, d
1Mx18
X = 19:0
X = a, b
X = a, b
Cypress Semiconductor Corporation
Document No: 001-07844 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 20, 2006
[+] Feedb
PRELIMINARY
Selection Guide
CY7C1330AV25-250
CY7C1332AV25-250
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.0
600
280
CY7C1330AV25
CY7C1332AV25
CY7C1330AV25-200
CY7C1332AV25- 200
2.25
550
260
Unit
ns
mA
mA
Pin Configurations
119-Ball BGA (14 x 22 x 2.4 mm)
CY7C1330AV25 (512K x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
NC
V
DDQ
2
A
A
A
DQ
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
3
A
A
A
V
SS
V
SS
V
SS
BWS
c
V
SS
V
REF
V
SS
BWS
d
V
SS
V
SS
V
SS
M
1
A
TDI
4
NC
NC
V
DD
ZQ
CE
OE
NC
NC
V
DD
K
K
WE
A0
A1
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWS
b
V
SS
V
REF
V
SS
BWS
a
V
SS
V
SS
V
SS
M
2
A
TDO
6
A
A
A
DQ
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DQ
a
A
NC
NC
7
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
ZZ
V
DDQ
DQ
d
DQ
d
DQ
d
DQ
d
A
NC
TMS
CY7C1332AV25 (1M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC
NC
V
DDQ
2
A
A
A
NC
DQ
b
NC
DQ
b
NC
V
DD
DQ
b
3
A
A
A
V
SS
V
SS
V
SS
BWS
b
V
SS
V
REF
V
SS
NC
V
SS
V
SS
V
SS
M
1
A
TDI
4
NC
NC
V
DD
ZQ
CE
OE
NC
NC
V
DD
K
K
WE
A0
A1
V
DD
NC
TCK
5
A
A
A
V
SS
V
SS
V
SS
NC
V
SS
V
REF
V
SS
BWS
a
V
SS
V
SS
V
SS
M
2
A
TDO
6
A
A
A
DQ
a
NC
DQ
a
NC
DQ
a
V
DD
NC
DQ
a
NC
DQ
a
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
NC
V
DDQ
NC
DQ
a
NC
ZZ
V
DDQ
NC
DQ
b
NC
DQ
b
A
A
TMS
Document No: 001-07844 Rev. *A
Page 2 of 19
[+] Feedb
PRELIMINARY
Pin Definitions
Name
A
BWS
a
BWS
b
BWS
c
BWS
d
WE
K,K
CE
OE
I/O Type
Input-
Synchronous
Input-
Synchronous
Description
CY7C1330AV25
CY7C1332AV25
Address Inputs used to select one of the address locations.
Sampled at the rising
edge of the K.
Byte Write Select Inputs, active LOW.
Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
a
controls DQ
a
, BWS
b
controls DQ
b
,
BWS
c
controls DQ
c
, BWS
d
controls DQ
d
.
Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This signal must
be asserted LOW to initiate a write sequence and high to initiate a read sequence.
Clock Inputs.
Used to capture all synchronous inputs to the device.
Chip Enable Input, active LOW.
Sampled on the rising edge of CLK. Used to
select/deselect the device.
Output Enable, active LOW.
Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[x:0]
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQ
a
–DQ
d
are placed in
a tri-state condition. The outputs are automatically tri-stated during the data portion of
a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE. DQ a,b,c,d are 9 bits wide
Mode control pins, used to set the proper read protocol.
For specified device
operation, M
1
must be connected to V
SS
, and M
2
must be connected to V
DD
or V
DDQ
.
These mode pins must be set at power-up and cannot be changed during device
operation.
ZZ “sleep” Input.
This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
Output Impedance Matching Input.
This input is used to tune the device outputs to
the system data bus impedance. Q
[x:0]
output impedance are set to 0.2 x RQ, where
RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
DDQ
, which enables the minimum impedance mode. This pin
cannot be connected directly to GND or left unconnected.
Power supply inputs to the core of the device.
For this device, the V
DD
is 2.5V.
Power supply for the I/O circuitry.
For this device, the V
DDQ
is 1.5V.
Reference Voltage Input.
Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Ground for the device.
Should be connected to ground of the system.
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK.
Serial data-in to the JTAG circuit.
Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine.
Sampled on the rising edge
of TCK.
Serial clock to the JTAG circuit.
No connects.
Input-
Synchronous
Input-
Differential Clock
Input-
Synchronous
Input-
Asynchronous
DQ
a
DQ
b
DQ
c
DQ
d
I/O-
Synchronous
M
1,
M
2
Read Protocol Mode
Pins
ZZ
ZQ
Input-
Asynchronous
Input
V
DD
V
DDQ
V
REF
V
SS
TDO
TDI
TMS
TCK
NC
Power Supply
I/O Power Supply
Input-
Reference Voltage
Ground
JTAG serial output
Synchronous
JTAG serial input
Synchronous
Test Mode Select
Synchronous
JTAG serial clock
–
Document No: 001-07844 Rev. *A
Page 3 of 19
[+] Feedb
PRELIMINARY
Introduction
Functional Overview
The CY7C1330AV25 and CY7C1332AV25 are synchronous-
pipelined Late Write SRAMs running at speeds up to 250 MHz.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
CO
) is 2.0 ns
(250-MHz device).
Accesses can be initiated by asserting Chip Enable (CE) on
the rising edge of the clock. The address presented to the
device will be latched on this edge of the clock. The access
can either be a read or write operation, depending on the
status of the Write Enable (WE). BWS
[d:a]
can be used to
conduct individual byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed late
write circuitry.
All operations (Reads, Writes, and Deselects) are pipelined.
Pipelined Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) Chip Enable (CE) is asserted active
and (2) the Write Enable input signal (WE) is asserted HIGH.
The address presented to the address inputs is latched into
the Address Register and presented to the memory core and
control logic. The control logic determines that a read access
is in progress and allows the requested data to propagate to
the input of the output register. At the rising edge of the next
clock the requested data is allowed to propagate through the
output register and onto the data bus within 2.0 ns (250-MHz
device) provided OE is active LOW. After the first clock of the
read access the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. During the second
clock, a subsequent operation (Read/Write/Deselect) can be
initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, its output will tri-state following the next clock
rise.
Bypass Read Operation
Bypass read operation occurs when the last write operation is
followed by a read operation where write and read addresses
are identical. The data outputs are provided from the data in
registers rather than the memory array. This operation occurs
on a byte to byte basis. If only one byte is written during a write
operation and a read operation is performed on the same
address; then a partial bypass read operation is performed
since the new byte data will be from the datain registers while
the remaining bytes are from the memory array.
Late Write Accesses
The Late Write feature allows for the write data to be presented
one cycle later after the access is started. This feature elimi-
nates one bus-turnaround cycle which is necessary when
going from a read to a write in an ordinary pipelined
Synchronous Burst SRAM.
Write access is initiated when the following conditions are
satisfied at clock rise: (1) CE is asserted active and (2) the
write signal WE is asserted LOW. The address presented to
Document No: 001-07844 Rev. *A
CY7C1330AV25
CY7C1332AV25
A
x
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
The data lines are automatically tri-stated regardless of the
state of the OE input signal when a write is detected. This
allows the external logic to present the data on DQ and DQP
(DQ
[a:b]
for CY7C1332AV25 and DQ
[a:d]
for CY7C1330AV25).
In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ (or a subset
for byte write operations, see Write Cycle Description table for
details) inputs is latched into the device and the write is
complete.
The data written during the Write operation is controlled by
BWS (BWS
[a:d]
for CY7C1330AV25 and BWS
[a:b]
for
CY7C1332AV25) signals. The CY7C1330AV25 and
CY7C1332AV25 provide byte write capability that is described
in the Write Cycle Description table. Asserting the Write
Enable input (WE) with the selected Byte Write Select (BWS)
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
Synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Because the CY7C1330AV25/CY7C1332AV25 is a common
I/O device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQ is
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Power-up/Power-down Supply Voltage Sequencing
The power-up and power-down supply voltage application
recommendations are as follows:
Power-up: V
SS
, V
DD
, V
DDQ
, V
REF
, V
IN
.
Power-down: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
.
V
DDQ
can be applied/removed simultaneously with V
DD
as
long as V
DDQ
does not exceed V
DD
by more than 0.5V.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
SS
to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±10% is between 175Ω and 350Ω
,
with
V
DDQ
=1.5V. The output impedance is adjusted every 1024
cycles to adjust for drifts in supply voltage and temper-
ature.The output buffers can also be programmed in a
minimum impedance configuration by connecting ZQ to V
DD
.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
Page 4 of 19
[+] Feedb
PRELIMINARY
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE must remain inactive for the duration of
t
ZZREC
after the ZZ input returns LOW.
CY7C1330AV25
CY7C1332AV25
Cycle Description Truth Table
[1, 2, 3, 4, 5]
Operation Address Used CE
Deselected External
Begin Read External
Begin Write External
Sleep Mode
-
1
0
0
X
WE BWS
x
CLK ZZ
X
1
0
X
X
X
Valid
X
L-H
L-H
L-H
X
0
0
0
1
Comments
I/Os tri-state following next recognized clock.
Address latched. Data driven out on the next rising edge of the clock.
Address latched, data presented to the SRAM on the next rising
edge of the clock.
Power down mode.
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > V
IH
ZZ > V
IH
ZZ < V
IL
2t
CYC
Min.
Max.
128
2t
CYC
Unit
mA
ns
ns
Write Cycle Descriptions
[1, 2]
Function (CY7C1330AV25)
Read
Write Byte 0 – DQ
a
Write Byte 1 – DQ
b
Write Bytes 1, 0
Write Byte 2 – DQ
c
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQ
d
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
Abort Write All Bytes
WE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BW
d
X
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
BW
c
X
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
BW
b
X
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
BW
a
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Write Cycle Descriptions
[1, 2]
Function (CY7C1332AV25)
Read
Write Byte 0 – DQ
a
Write Byte 1 – DQ
b
Write All Bytes
Abort Write All Bytes
WE
1
0
0
0
0
BW
b
X
1
0
0
1
BW
a
X
0
1
0
1
Notes:
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW. BWSx = 0 signifies at least one Byte Write Select is active, BWSx = Valid signifies that the desired byte write
selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWSx. See Write Cycle Description table for details.
3. The DQ pins are controlled by the current cycle and the OE signal.
4. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
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