Digital circuit sound and light control stair delay switch circuit (2)

The introduced sound and light stairway delay switch has all the advantages of the above circuit, and also saves
the only semiconductor diode, thereby achieving full integration. The circuit is shown in Figure 162.
    This circuit mainly uses a 2-input terminal digital integrated circuit called NAND, in which NAND gate III forms the
microphone amplifier circuit; NAND gate IV forms the "AND gate" control of light control and amplification signal; NAND r] 1 and NAND gate
II form a monostable delay control circuit. The entire circuit is powered by resistor R. Falling earthworm, VD2 half-wave viper current,
capacitor C. Filtered supply.
    In the static state, the input terminal R of NAND gate III is connected to the positive power supply, so the output terminal pin ⑩ is low-voltage. The logic of pin Ⅳ of NAND gate
"." makes pin ⑥ of the small theory full of logic "." during the day. It is the logic "l" of the black night, and its input terminal ⑧ is the logic
"1" of the total input m. The logic of the input terminals ⑤ and ⑤ of the NAND gate II is '()", so that the output terminal ④ inputs logic "1". Therefore, at this time, the
input terminals ① and ② of the NAND gate J J Ej are all logic "()" 1", the output terminal ③ is logic "o". When the alternating current is a positive half cycle (i.e. j, negative
), the thyristor VT has no conduction condition and is cut off. At this time, the half-wave rectification of the alternating current VD2 provides power for the circuit. When
When the alternating current is negative half (i.e. negative at the top and positive at the bottom), the resistors R, R, are connected in series to provide trigger current for VT. Because the ③
pin input rIJ logic is "inactive". ", the directional current flows through MA, VD1 and the ③ pin of NAND gate l to ground. The VT gate is at a low level and VT
is turned off, so the light E does not light up.
    When microphone B receives the environmental sound wave signal, it The corresponding electrical signal is output, coupled through (., and sent to
the input terminals ⑧, ⑨~j of the NAND gate III. The amplified signal is output from the ⑩ pin. When the peak value of the positive half cycle of the frequency signal exceeds
the closing value of the NAND gate iIVfrJ Normally, NAND gate IV flips, and pin ⑩ outputs logic "." (Assume that the environment is dark at this time, and
pin ⑩ is the logic level "l"), so pin ③ of NAND gate I outputs logic "1", and the diode VD1 cut off, VT
​​is turned on by R getting the trigger current m, and the lamp E lights up. At the same time, the island level of pin ③ passes through
the coupling of c, so that the input terminals ⑤ and ⑥ of gate Ⅱ are also island level, so the output terminal ④ pin outputs logic
"." and is directly added to the ② pin of NAND rlr. At this time, even if the level of ⑩ pin has changed with the audio, the ①
pin of NAND gate I is Logic "1", but because pin ② is logic ".", pin ③ outputs logic "l",
so the light E can still remain lit. While the light is on, the high level of pin ③ passes through R . Charge fU to c,
so that the voltage across the capacitor continues to increase. Therefore, the levels of the input terminals ⑤ and ⑥ of the NAND gate II continue to decrease.
When the level is lower than the NAND rJ input value H, ④ The pin outputs logic "l". If the environment is silent at this time, pin ① is also logic "l". Just pin ③ outputs logic "o", the thyristor VT is turned off, and the light E goes out. If there is sound
again , the light
It can be lit again. The duration of the light is mainly determined by the electric time constant of R; and G.
When the lamp in this circuit is lit, the current flowing through the bulb is also half-wave alternating current, which is beneficial to extending the service life of the bulb.
    R, It forms a light control circuit with the photodiode VDP #i , and the resistance of VD3 is high early, so that pin ⑩ is a high level
"1". At this time, the level of pin ⑩ of the output terminal of NAND gate IV only depends on the voltage of pin ⑥. The level changes, that is to say, it only
depends on the environment and the sound irii. During the day, VD3 is low in voltage, so that the ⑥ pin is in the logic "o", thus
blocking the NAND gate IV, so that the thyristor VT is not controlled by the environmental sound. Lamp E never lights up.