DS2155
T1/E1/J1 Single-Chip Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS2155 is a software-selectable T1, E1, or J1
single-chip transceiver (SCT) for short-haul and
long-haul applications. The DS2155 is composed of a
line interface unit (LIU), framer, HDLC controllers,
and a TDM backplane interface, and is controlled by
an 8-bit parallel port configured for Intel or Motorola
bus operations. The DS2155 is pin and software
compatible with the DS2156.
The LIU is composed of transmit and receive
interfaces and a jitter attenuator. The transmit
interface is responsible for generating the necessary
waveshapes for driving the network and providing
the correct source impedance depending on the type
of media used. T1 waveform generation includes
DSX-1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75Ω
coax and 120Ω twisted cables. The receive interface
provides network termination and recovers clock and
data from the network.
FEATURES
Complete T1/DS1/ISDN-PRI/J1 Transceiver
Functionality
Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
Long-Haul and Short-Haul Line Interface for
Clock/Data Recovery and Waveshaping
CMI Coder/Decoder for Optical I/F
Crystal-Less Jitter Attenuator
Fully Independent Transmit and Receive
Functionality
Dual HDLC Controllers
Programmable BERT Generator and Detector
Internal Software-Selectable Receive and
Transmit-Side Termination Resistors for
75Ω/100Ω/120Ω T1 and E1 Interfaces
Dual Two-Frame Elastic-Store Slip Buffers that
Connect to Asynchronous Backplanes Up to
16.384MHz
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
Features continued in Section
3.
APPLICATIONS
T1/E1/J1 Line Cards
Switches and Routers
Add-Drop Multiplexers
ORDERING INFORMATION
PART
DS2155L
DS2155L+
DS2155LN
DS2155LN+
DS2155G
DS2155G+
DS2155GN
DS2155GN
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
100 LQFP
100 LQFP
100 LQFP
100 LQFP
100 CSBGA
100 CSBGA
100 CSBGA
100 CSBGA
T1/E1/J1
NETWORK
DS2155
T1/E1/J1
SCT
BACKPLANE
TDM
+
Denotes a lead-free/RoHS-compliant package.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 080607
DS2155
1. TABLE OF CONTENTS
1.
1.1
1.2
2.
3.
3.1
3.2
4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
5.
5.1
6.
TABLE OF CONTENTS ............................................................................................................................2
T
ABLE OF
F
IGURES
........................................................................................................................................6
T
ABLE OF
T
ABLES
..........................................................................................................................................7
DATA SHEET REVISION HISTORY .....................................................................................................8
MAIN FEATURES....................................................................................................................................10
F
UNCTIONAL
D
ESCRIPTION
.........................................................................................................................13
B
LOCK
D
IAGRAM
.........................................................................................................................................15
PIN FUNCTION DESCRIPTION ...........................................................................................................19
T
RANSMIT
S
IDE
...........................................................................................................................................19
R
ECEIVE
S
IDE
..............................................................................................................................................21
P
ARALLEL
C
ONTROL
P
ORT
P
INS
.................................................................................................................24
E
XTENDED
S
YSTEM
I
NFORMATION
B
US
......................................................................................................25
U
SER
O
UTPUT
P
ORT
P
INS
............................................................................................................................26
JTAG T
EST
A
CCESS
P
ORT
P
INS
...................................................................................................................27
L
INE
I
NTERFACE
P
INS
..................................................................................................................................28
S
UPPLY
P
INS
................................................................................................................................................29
L
AND
G P
ACKAGE
P
INOUT
.........................................................................................................................30
10
MM
CSBGA P
IN
C
ONFIGURATION
......................................................................................................32
PARALLEL PORT ...................................................................................................................................33
R
EGISTER
M
AP
............................................................................................................................................33
PROGRAMMING MODEL.....................................................................................................................39
6.1 P
OWER
-U
P
S
EQUENCE
.................................................................................................................................40
6.1.1
Master Mode Register.........................................................................................................................40
6.2 I
NTERRUPT
H
ANDLING
................................................................................................................................41
6.3 S
TATUS
R
EGISTERS
......................................................................................................................................41
6.4 I
NFORMATION
R
EGISTERS
...........................................................................................................................42
6.5 I
NTERRUPT
I
NFORMATION
R
EGISTERS
........................................................................................................42
7.
8.
9.
9.1
9.2
9.3
9.4
10.
10.1
10.2
10.3
11.
11.1
SPECIAL PER-CHANNEL REGISTER OPERATION.......................................................................43
CLOCK MAP ............................................................................................................................................45
T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS............................................46
T1 C
ONTROL
R
EGISTERS
.............................................................................................................................46
T1 T
RANSMIT
T
RANSPARENCY
...................................................................................................................51
AIS-CI
AND
RAI-CI G
ENERATION AND
D
ETECTION
..................................................................................51
T1 R
ECEIVE
-S
IDE
D
IGITAL
-M
ILLIWATT
C
ODE
G
ENERATION
.....................................................................52
E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS............................................55
E1 C
ONTROL
R
EGISTERS
.........................................................................................................................55
A
UTOMATIC
A
LARM
G
ENERATION
.........................................................................................................59
E1 I
NFORMATION
R
EGISTERS
..................................................................................................................60
COMMON CONTROL AND STATUS REGISTERS ..........................................................................62
T1/E1 S
TATUS
R
EGISTERS
......................................................................................................................63
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DS2155
12.
13.
13.1
14.
I/O PIN CONFIGURATION OPTIONS.................................................................................................69
LOOPBACK CONFIGURATION ..........................................................................................................71
P
ER
-C
HANNEL
L
OOPBACK
......................................................................................................................73
ERROR COUNT REGISTERS ...............................................................................................................75
14.1
L
INE
-C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(LCVCR).............................................................................76
14.1.1 T1 Operation.......................................................................................................................................76
14.1.2 E1 Operation.......................................................................................................................................76
14.2
P
ATH
C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(PCVCR) ............................................................................78
14.2.1 T1 Operation.......................................................................................................................................78
14.2.2 E1 Operation.......................................................................................................................................78
14.3
F
RAMES
O
UT
-
OF
-S
YNC
C
OUNT
R
EGISTER
(FOSCR)..............................................................................79
14.3.1 T1 Operation.......................................................................................................................................79
14.3.2 E1 Operation.......................................................................................................................................79
14.4
E-B
IT
C
OUNTER
(EBCR).........................................................................................................................80
15.
16.
DS0 MONITORING FUNCTION ...........................................................................................................81
SIGNALING OPERATION .....................................................................................................................83
16.1
R
ECEIVE
S
IGNALING
...............................................................................................................................83
16.1.1 Processor-Based Signaling.................................................................................................................83
16.1.2 Hardware-Based Receive Signaling ...................................................................................................84
16.2
T
RANSMIT
S
IGNALING
.............................................................................................................................89
16.2.1 Processor-Based Mode .......................................................................................................................89
16.2.2 Software Signaling Insertion-Enable Registers, E1 CAS Mode..........................................................93
16.2.3 Software Signaling Insertion-Enable Registers, T1 Mode..................................................................95
16.2.4 Hardware-Based Mode.......................................................................................................................95
17.
17.1
18.
19.
PER-CHANNEL IDLE CODE GENERATION ....................................................................................96
I
DLE
-C
ODE
P
ROGRAMMING
E
XAMPLES
..................................................................................................97
CHANNEL BLOCKING REGISTERS ................................................................................................101
ELASTIC STORES OPERATION........................................................................................................104
19.1
R
ECEIVE
S
IDE
........................................................................................................................................107
19.1.1 T1 Mode ............................................................................................................................................107
19.1.2 E1 Mode............................................................................................................................................107
19.2
T
RANSMIT
S
IDE
.....................................................................................................................................107
19.2.1 T1 Mode ............................................................................................................................................108
19.2.2 E1 Mode............................................................................................................................................108
19.3
E
LASTIC
S
TORES
I
NITIALIZATION
.........................................................................................................108
19.4
M
INIMUM
D
ELAY
M
ODE
.......................................................................................................................108
20.
21.
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) ...................................................109
T1 BIT-ORIENTED CODE (BOC) CONTROLLER..........................................................................110
21.1
T
RANSMIT
BOC.....................................................................................................................................110
Transmit a BOC ..............................................................................................................................................110
21.2
R
ECEIVE
BOC .......................................................................................................................................110
Receive a BOC.................................................................................................................................................110
22.
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) ......................113
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DS2155
22.1
22.2
22.3
23.
M
ETHOD
1: H
ARDWARE
S
CHEME
.........................................................................................................113
M
ETHOD
2: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
D
OUBLE
-F
RAME
..............................................113
M
ETHOD
3: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
CRC4 M
ULTIFRAME
........................................116
HDLC CONTROLLERS ........................................................................................................................126
23.1
B
ASIC
O
PERATION
D
ETAILS
..................................................................................................................126
23.2
HDLC C
ONFIGURATION
........................................................................................................................126
23.2.1 FIFO Control....................................................................................................................................130
23.3
HDLC M
APPING
....................................................................................................................................131
23.3.1 Receive ..............................................................................................................................................131
23.3.2 Transmit ............................................................................................................................................133
23.3.3 FIFO Information .............................................................................................................................138
23.3.4 Receive Packet-Bytes Available........................................................................................................138
23.3.5 HDLC FIFOs ....................................................................................................................................139
23.4
R
ECEIVE
HDLC C
ODE
E
XAMPLE
..........................................................................................................140
23.5
L
EGACY
FDL S
UPPORT
(T1 M
ODE
)......................................................................................................140
23.5.1 Overview ...........................................................................................................................................140
23.5.2 Receive Section .................................................................................................................................140
23.5.3 Transmit Section ...............................................................................................................................142
23.6
D4/SLC-96 O
PERATION
........................................................................................................................142
24.
LINE INTERFACE UNIT (LIU) ...........................................................................................................143
24.1
LIU O
PERATION
....................................................................................................................................143
24.2
R
ECEIVER
..............................................................................................................................................143
24.2.1 Receive Level Indicator and Threshold Interrupt .............................................................................144
24.2.2 Receive G.703 Synchronization Signal (E1 Mode)...........................................................................144
24.2.3 Monitor Mode ...................................................................................................................................144
24.3
T
RANSMITTER
.......................................................................................................................................145
24.3.1 Transmit Short-Circuit Detector/Limiter ..........................................................................................145
24.3.2 Transmit Open-Circuit Detector.......................................................................................................145
24.3.3 Transmit BPV Error Insertion ..........................................................................................................145
24.3.4 Transmit G.703 Synchronization Signal (E1 Mode).........................................................................145
24.4
MCLK P
RESCALER
...............................................................................................................................146
24.5
J
ITTER
A
TTENUATOR
.............................................................................................................................146
24.6
CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
...............................................................................................146
24.7
LIU C
ONTROL
R
EGISTERS
.....................................................................................................................147
24.8
R
ECOMMENDED
C
IRCUITS
.....................................................................................................................156
24.9
C
OMPONENT
S
PECIFICATIONS
...............................................................................................................158
25.
26.
26.1
26.2
26.3
26.4
26.5
26.6
27.
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION......................163
BERT FUNCTION ..................................................................................................................................170
S
TATUS
..................................................................................................................................................170
M
APPING
...............................................................................................................................................170
BERT R
EGISTER
D
ESCRIPTIONS
...........................................................................................................172
BERT R
EPETITIVE
P
ATTERN
S
ET
..........................................................................................................176
BERT B
IT
C
OUNTER
.............................................................................................................................177
BERT E
RROR
C
OUNTER
........................................................................................................................178
PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)................................................180
27.1
N
UMBER
-
OF
-E
RRORS
R
EGISTERS
..........................................................................................................182
27.1.1 Number-of-Errors Left Register........................................................................................................183
28.
INTERLEAVED PCM BUS OPERATION (IBO) ...............................................................................184
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DS2155
28.1
28.2
29.
30.
31.
32.
33.
34.
34.1
34.2
34.3
34.4
34.5
34.6
35.
35.1
35.2
36.
37.
37.1
37.2
37.3
37.4
37.5
38.
38.1
38.2
C
HANNEL
I
NTERLEAVE
.........................................................................................................................184
F
RAME
I
NTERLEAVE
..............................................................................................................................184
EXTENDED SYSTEM INFORMATION BUS (ESIB) .......................................................................187
PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER ........................................................191
FRACTIONAL T1/E1 SUPPORT .........................................................................................................191
USER-PROGRAMMABLE OUTPUT PINS........................................................................................193
TRANSMIT FLOW DIAGRAMS .........................................................................................................194
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .................................199
D
ESCRIPTION
.........................................................................................................................................199
I
NSTRUCTION
R
EGISTER
........................................................................................................................202
T
EST
R
EGISTERS
....................................................................................................................................204
B
OUNDARY
S
CAN
R
EGISTER
.................................................................................................................204
B
YPASS
R
EGISTER
.................................................................................................................................204
I
DENTIFICATION
R
EGISTER
....................................................................................................................204
FUNCTIONAL TIMING DIAGRAMS.................................................................................................208
T1 M
ODE
...............................................................................................................................................208
E1 M
ODE
...............................................................................................................................................213
OPERATING PARAMETERS ..............................................................................................................222
AC TIMING PARAMETERS AND DIAGRAMS ...............................................................................224
M
ULTIPLEXED
B
US
AC C
HARACTERISTICS
..........................................................................................224
N
ONMULTIPLEXED
B
US
AC C
HARACTERISTICS
...................................................................................227
R
ECEIVE
-S
IDE
AC C
HARACTERISTICS
..................................................................................................230
B
ACKPLANE
C
LOCK
T
IMING
: AC C
HARACTERISTICS
.........................................................................233
T
RANSMIT
AC C
HARACTERISTICS
........................................................................................................234
PACKAGE INFORMATION ................................................................................................................237
100-P
IN
LQFP (56-G5002-000) ............................................................................................................237
100-B
ALL
CSBGA (56-G6008-001) .....................................................................................................238
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Microcontroller MCU
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