IS61LPD102418A-200B3I datasheet, PDF

Datasheet> All Categories > storage> storage> IS61LPD102418A-200B3I

IS61LPD102418A-200B3I: DescriptionCache SRAM, 1MX18, 3.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165; Categorystorage storage; File Size476KB，29 Pages; ManufacturerISSI(Integrated Silicon Solution Inc.); Websitehttp://www.issi.com/

Download Datasheet Parametric View All

IS61LPD102418A-200B3I Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	IS61LPD102418A-200B3I	-	-	View	Buy Now

IS61LPD102418A-200B3I Overview

Cache SRAM, 1MX18, 3.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165

IS61LPD102418A-200B3I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Objectid	1983795257
Parts packaging code	BGA
package instruction	TBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
Country Of Origin	Mainland China, Taiwan
ECCN code	3A991.B.2.A
YTEOL	5.87
Maximum access time	3.1 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	CACHE SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.075 A
Minimum standby current	3.14 V
Maximum slew rate	0.475 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

Preview

Download Datasheet

View All

IS61VPD51236a IS61VPD102418a

IS61lPD51236a IS61lPD102418a

512K x 36, 1024K x 18

18Mb SYNCHRONOUS PIPElINED,

DOUBlE CYClE DESElECT STaTIC RaM

JUlY 2008

FEaTURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth ex-

pansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Double cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

LPD: V

3.3V + 5%,

ddq

3.3V/2.5V + 5%

VPD: V

2.5V + 5%,

ddq

2.5V + 5%

• JEDEC 100-Pin TQFP and 165-pin PBGA

package

• Lead-free available

DESCRIPTION

The

ISSI

IS61LPD/VPD51236A and IS61LPD/VP-

D102418A are high-speed, low-power synchronous

static RAMs designed to provide burstable, high-performance

memory for communication and networking applications.

The IS61LPD/VPD51236A is organized as 524,288 words

by 36 bits, and the IS61LPD/VPD102418A is organized

as 1,048,576 words by 18 bits. Fabricated with

ISSI

advanced CMOS technology, the device integrates a

2-bit burst counter, high-speed SRAM core, and high-

drive capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte write

enable (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FaST aCCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

250

2.6

250

200

3.1

200

Units

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. C

07/08/08

Recommended Resources

Eight-position light-touch electronic interlock switch circuit

Water level detection control circuit circuit diagram

Boost circuit with low battery voltage detection

Automatic air freshener circuit

Dual-channel integrated twin amplifier circuit

820e computer motherboard circuit diagram_51

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components