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PI6LC48P0301AZHEX

Description
Clock Generators & Support Products 3-Output LVPECL Net working Clock Gen
Categorysemiconductor    Analog mixed-signal IC   
File Size945KB,12 Pages
ManufacturerDiodes Incorporated
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Clock Generators & Support Products 3-Output LVPECL Net working Clock Gen

PI6LC48P0301AZHEX Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerDiodes Incorporated
Product CategoryClock Generators & Support Products
PackagingReel
Factory Pack Quantity3500
PI6LC48P02
2-Output LVPECL Fibre Channel (FC) and Ethernet Clock Generator
Features
ÎÎ
Two differential LVPECL output pairs
ÎÎ
Selectable crystal oscillator interface or LVCMOS/LVTTL
Description
The PI6LC48P02 is a 2-output LVPECL synthesizer optimized
to generate Fibre Channel, Ethernet and storage reference clock
frequencies and is a member of Pericom’s HiFlex family of high
performance clock solutions. Using a 26.5625MHz crystal, the
most popular Fibre Channel (FC) frequencies can be generated
based on the settings of 2 frequency select pins. Using 25MHz
Xtal, most Ethenrnet frequencies inckuding 100MHz can be
generated, while using 26.041667MHz Xtal, 156.25MHz can be
generated for Networking applications.
The PI6LC48P02 uses Pericom’s proprietary low phase noise
PLL technology to achieve ultra low phase jitter, it is ideal for
Networking, data center, and storage systems.
single-ended clock input
ÎÎ
Supports the following output frequencies:
ÎÎ
Ethernet: 50MHz, 100MHz, 150MHz, 156.25MHz,
200MHz
ÎÎ
Fibre Channel: 53.125MHz, 106.25MHz, 159.375MHz,
187.5MHz, 212.5MHz
ÎÎ
RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(12kHz – 20MHz): 0.28ps (typical)
– 20MHz): 0.32ps (typical)
ÎÎ
RMS phase jitter @ 100MHz, using a 25MHz crystal (12kHz
ÎÎ
RMS phase jitter @ 156.25MHz, using a 26.041667MHz
crystal (12kHz – 20MHz): 0.30ps (typical)
Applications
ÎÎ
Networking and Data Center Server systems
ÎÎ
Fibre Channel (FC) and Storage systems
ÎÎ
Full 3.3V or 2.5V supply modes
ÎÎ
Industrial operating temperature
ÎÎ
Available in lead-free package: 20-TSSOP
Block Diagram
XTAL_IN
XTAL_OUT
Ref_IN
OSC
PFD
VCO
/N
CLK0
CLK0#
IN_SEL
M
PLL_ByPass
N_SEL[0:1]
CLK1
CLK1#
M_reset
15-0102
1
www.pericom.com
PI6LC48P02
Rev. C
08/13/15
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