PI6C39911
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer -
SuperClock
®
Features
• All output pair skew <100ps typical (250 Max.)
• 12.5 MHz to 133 MHz output operation
• 3.125 MHz to 133 MHz input operation (input as low as 3.125
MHz for 4x operation, or 6.25 MHz for 2x operation)
• User-selectable output functions
— Selectable skew to 18ns
— Inverted and non-inverted
— Operation at ½ and ¼ input frequency
— Operation at 2X and 4X input frequency
• Zero input-to-output delay
• 50% duty-cycle outputs
• Inputs are 5V Tolerant
• LVTTL outputs drive 50-Ohm terminated lines
• Operates from a single 3.3V supply
• Low operating current
• 32-pin PLCC package (available in pb-free and green)
• Jitter < 200ps peak-to-peak (< 25ps RMS)
Description
The PI6C39911 offers selectable control over system clock func-
tions. These multiple-output clock drivers provide the system
integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual drivers,
arranged as four pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as low as 50-Ohms
while delivering minimal and specified output skews and full-swing
logic levels.
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow distri-
bution of a low-frequency clock that can be multiplied by two or four
at the clock destination. This feature allows flexibility and simpli-
fies system timing distribution design for complex high-speed
systems.
Logic Block Diagram
Test
Filter
Pin Configuration
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
Select Inputs
(three level)
4Q1
Skew
Select
Matrix
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
5
6
7
8
9
10
11
12
13
4
3
2
REF
GND
TEST
2F1
1
32 31
30
3F0
FS
V
CCQ
FB
Phase
Freq.
DET
VCO and
Time Unit
Generator
29
28
32 Pin
J
27
26
25
24
23
22
21
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
14 15 16 17 18 19
20
08-0298
1
V
CCN
FB
V
CCN
2Q1
2Q0
3Q1
3Q0
PS8497I
11/06/08
PI6C39911
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer
- SuperClock
®
Pin Descriptions
Signal
Name
REF
FB
FS
1F0, 1F1
2F 0, 2F 1
3F 0, 3F 1
4F 0, 4F 1
TEST
1Q0, 1Q1
2Q 0, 2Q 1
3Q 0, 3Q 1
4Q 0, 4Q 1
V
CCN
V
CCQ
GND
I/O
I
I
I
I
I
I
I
I
O
O
O
O
De s cription
Reference frequency input supplies the frequency and timing against which all functional variation is measured.
PLL feedback input (typically connected to one of the eight outputs)
Three- level frequency range select. see Table 1.
Three- level function select inputs for output pair 1 (1Q0, 1Q1). see Table 2.
Three- level function select inputs for output pair 2 (2Q0, 2Q1). see Table 2.
Three- level function select inputs for output pair 3 (3Q0, 3Q1). see Table 2.
Three- level function select inputs for output pair 4 (4Q0, 4Q1). see Table 2.
Three- level select. See test mode section under the block diagram descriptions
Output pair 1. see Table 2
Output pair 2. see Table 2
Output pair 3. see Table 2
Output pair 4. see Table 2
PWR Power supply for output drivers
PWR Power supply for internal circuitry
PWR Ground
Table 1. Frequency Range Select and t
U
Calculation
(1)
FS
(1,2)
LOW
MID
HIGH
F
NOM
(M Hz)
M in.
12.5
25
40
M ax.
30
50
133
t
U
=
Table 2. Programmable Skew Configurations
(1)
Function Se le cts
1F1, 2F1,
3F1, 4F1
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
1F0, 2F0,
3F0, 4F0
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
Output Functions
1Q0, 1Q1,
2Q0, 2Q1
–4t
U
–3t
U
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
3Q0, 3Q1
4Q0, 4Q1
1
f
NOM
× N
whe re N=
44
26
16
Approximate
Fre q. (M Hz) at
which t
U
= 1.0ns
22.7
38. 5
62.5
Divide by 2 Divide by 2
–6t
U
–4t
U
–2t
U
0t
U
+2t
U
+4t
U
+6t
U
Divide by 4
–6t
U
–4t
U
–2t
U
0t
U
+2t
U
+4t
U
+6t
U
Inverted
Notes:
1. For all three-state inputs, HIGH indicates a connection to V
CC
, LOW indicates a connection to GND, and MID indicates an open
connection. Internal termination circuitry holds an unconnected input to V
CC
/2.
2. The level to be set on FS is determined by the “normal” operating frequency (f
NOM
) and Time Unit Generator (see Logic Block Diagram).
Nominal frequency (f
NOM
) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table
2). The frequency appearing at the REF and FB inputs will be f
NOM
when the output connected to FB is undivided. The frequency
of the REF and FB inputs will be f
NOM
/2 or f
NOM
/4 when the part is configured for a frequency multiplication by using a divided output
as the FB input.
08-0298
2
PS8497I
11/06/08
PI6C39911
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer
- SuperClock
®
Maximum Ratings
Storage Temperature ..................................... –65°C to +150°C
Ambient Temperature with
Power Applied ............................................... –55°C to +125°C
Supply Voltage to Ground Potential ................ –0.5V to +5.0V
DC Input Voltage .............................................. –0.5V to +5.0V
Output Current into Outputs (LOW) .............................. 64mA
Static Discharge Voltage ............................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ......................................................... >200mA
Maximum Power Dissipation at T
A
=85°C
(2,3) ..............
0.80watts
Test Mode
The TEST input is a three-level input. In normal system operation,
this pin is connected to ground, allowing the PI6C39911 to operate
as explained briefly above (for testing purposes, any of the three
level inputs can have a removable jumper to ground, or be tied LOW
through a 100 Ohm resistor. This will allow an external tester to
change the state of these pins.)
If the TEST input is forced to its MID or HIGH state, the device will
operate with its internal phase locked loop disconnected, and input
levels supplied to REF will directly control all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of the
REF input.
Operating Range
Range
Commercial
Industrial
Ambie nt Te mpe rature
0°C to +70°C
–40°C to +85°C
V
CC
3 . 3 V ± 10 %
3 . 3 V ± 10 %
t
0
+1t
U
t
0
+2t
U
t
0
+3t
U
t
0
+4t
U
t
0
+5t
U
1Fx
2Fx
FB Input
REF Input
3Fx
4Fx
–6t
U
–4t
U
–3t
U
–2t
U
–1t
U
A)
A)
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
LL/HH
+6t
U
Divided
Invert
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
(3)
Note:
3. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID)
08-0298
3
t
0
+6t
U
t
0
–6t
U
t
0
–5t
U
t
0
–4t
U
t
0
–3t
U
t
0
–2t
U
t
0
–1t
U
t
0
PS8497I
11/06/08
PI6C39911
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer
- SuperClock
®
Capacitance
(6)
Parame te r
C
IN
De s cription
Input Capacitance
Te s t Conditions
T
A
= 25°C, f = 1MHz, V
CC
= 3.3V
M a x.
10
Units
pF
Electrical Characteristics
(Over the Operating Range)
Parame te r
V
OH
V
OL
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IH
I
IL
I
IHH
I
IMM
I
ILL
I
OS
I
CCQ
I
CCN
PD
De s cription
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(REF and FB inputs only)
Input LOW Voltage
(REF and FB inputs only)
Three- Level Input HIGH Voltage
(Test, FS, xFn)
(4)
Three- Level Input MID Voltage
(Test, FS, xFn)
(4)
Three- Level Input LOW Voltage
(Test, FS, xFn)
(4)
Input HIGH Leakage Current
(REF and FB inputs only)
Input LOW Leakage Current
(REF and FB inputs only)
Input HIGH Current (Test, FS, xFn)
Input MID Current (Test, FS, xFn)
Input LOW Current (Test, FS, xFn)
Short Circuit Current
(5)
Operating Current Used by Internal
Circuitry
Output Buffer Current per Output Pair
Power Dissipation per Output Pair
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
V
CC
= Max., V
IN
= Max.
V
CC
= Max., V
IN
= 0.4V
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN =
GND
V
CC
= Max., V
OUT
= GND (25°C only)
V
CCN
= V
CCQ
= Max.,
All Input Selects Open
Com'l
Mil/Ind
–50
–200
–200
95
100
19
104
mW
mA
–20
μ
A
200
50
Te s t Conditions
V
CC
= Min., I
OH
= –18mA
V
CC
= Min., I
OL
= 35mA
2.0
–0.5
0.87 V
CC
0.47 V
CC
0 .0
M in.
2.4
0.4 5
V
CC
0 .8
V
V
CC
0.53 V
CC
0.13 V
CC
20
M ax.
Units
V
CCN
= V
CCQ
= Max., I
OUT
= 0mA
All Input Selects Open, f
MAX
V
CCN
= V
CCQ
= Max., I
OUT
= 0mA
All Input Selects Open, f
MAX
Notes:
4. These inputs are normally wired to V
CC
, GND, or left unconnected (actual threshold voltages vary as a percentage of V
CC
).
Internal termination resistors hold unconnected inputs at V
CC
/2. If these inputs are switched, the function and timing of the
outputs may glitch and the PLL may require an additional t
LOCK
time before all data sheet limits are achieved.
5. PI6C39911 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
Room temperature only.
6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
7. Test measurement levels for the PI6C39911 are 1.5V to 1.5V. Test conditions assume signal transition times of 2ns or less and output
loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
8. Guaranteed by statistical correlation.
08-0298
4
PS8497I
11/06/08
PI6C39911
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer
- SuperClock
®
Switching Characteristics
(Over the Operating Range)
(2,7)
Parame te r
O perating
C lock
F requency
in MHz
D e s cription
F S = LO W
(1 , 2 )
F S = MID
(1 , 2 )
F S = HIGH
(1 , 2 )
PI6C39911-2
M in.
12.5
25
40
3.0
3.0
S ee Table 1
0.1
0.20
0.4
0.6
0.4
0.5
0.25
0.25
0.5
0.8
0.5
0.8
1.0
–0.3
–1.0
0.0
0.0
+0.3
+1.0
2.5
3.0
0.15
0.15
RMS
(8 )
P e a k - to - p e a k
( 8 )
1.0
1.0
1.5
1.5
0.5
25
200
0.15
0.15
1.0
1.0
–0.5
–1.0
0.0
0.0
f
N O M (1 , 2 )
t
R P W H
t
R P W L
t
U
t
S K E W P R
t
S K E W 0
t
S K E W 1
t
S K E W 2
t
S K E W 3
t
S K E W 4
t
D E V
t
P D
t
O D C V
t
P W H
t
P W L
t
O R I S E
t
O FA LL
t
L O C K
t
J R
30
50
133
PI6C39911-5
Typ. M ax.
30
50
133
12.5
25
40
3.0
3.0
S ee Table 1
0.1
0.25
0.6
0.5
0.5
0.5
0.25
0.5
0.7
1.0
0.7
1.0
1.25
+0.5
+1.0
2.5
3.0
1.5
1.5
0.5
25
200
0.15
0.15
1.0
1.0
–0.7
–1.2
0.0
0.0
Typ. M ax. M in.
Unit-
s
M in. Typ. M ax.
12.5
25
40
3.0
3.0
S ee Table 1
0.1
0.3
0.6
1.0
0.7
1.2
0.25
0.75
1.0
1.5
1.2
1.7
1.65
+0.7
+1.2
3.0
3.5
1.5
1.5
0.5
25
200
ms
ps
ns
30
50
133
ns
MHz
PI6C39911
REF P ulse Width HIGH
REF P ulse Width LO W
P rogrammable S kew Unit
Zero O utput Matched
- P air S kew (XQ 0, XQ 1)
(9 , 1 0 )
Zero O utput S kew (All O utputs)
(9 , 11 )
O utput S kew (Rise- Rise, F all- F all,
S ame C lass O utputs)
(9 , 1 3 )
O utput S kew (Rise- F all, N ominal- Inverted,
Divided- Divided)
(9 , 1 3 )
O utput S kew (Rise- Rise, F all- F all,
Different C lass O utputs)
(9 , 1 3 )
O utput S kew (Rise- F all, N ominal- Divided,
Divided- Inverted)
(9 , 1 3 )
Device- to- Device S kew
(8 , 1 4 )
P ropagation Delay, REF Rise to F B Rise
O utput Duty C ycle Variation
(1 5 )
O utput HIGH Time Deviation from 50%
(1 6 )
O utput LO W Time Deviation from 50%
(1 6 )
O utput Rise Time
(1 6 , 1 7 )
O utput F all Time
(1 6 , 1 7 )
P LL Lock Time
(1 8 )
C ycle- to- cycle
O utput Jitter
Notes:
9. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been
selected when all are loaded with 30pF and terminated with 50 ohms to V
CC
/2.
10. t
SKEWPR
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t
U
.
11. t
SKEW0
is defined as the skew between outputs when they are selected for 0t
U
. Other outputs are divided or inverted but not shifted.
12. C
L
= 0pF. For C
L
= 30pF, t
SKEW0
= 0.35ns.
13. There are three classes of outputs: Nominal (multiple of t
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx
and 4Qx only in Divide-by-2 or Divide-by-4 mode).
14. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
ambient temperature, air flow, etc.)
15. t
ODCV
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
SKEW2
and t
SKEW4
specifications.
16. Specified with outputs loaded with 30pF for the PI6C39911 devices. Devices are terminated through 50 Ohm to V
CC
/2. t
PWH
is measured
at 2.0V. t
PWL
is measured at 0.8V.
17. t
ORISE
and t
OFALL
measured between 0.8V and 2.0V.
18. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
08-0298
5
PS8497I
11/06/08
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