ISPPAC-CLK5520V-01TN100I datasheet, PDF

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ISPPAC-CLK5520V-01TN100I: DescriptionClock Drivers & Distribution PROGRAMMABLE CLOCK GENERATOR; Categorylogic logic; File Size423KB，49 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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ISPPAC-CLK5520V-01TN100I Overview

Clock Drivers & Distribution PROGRAMMABLE CLOCK GENERATOR

ISPPAC-CLK5520V-01TN100I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	QFP
package instruction	LFQFP, QFP100,.63SQ,20
Contacts	100
Reach Compliance Code	compliant
ECCN code	EAR99
series	5500
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
length	14 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	100
Actual output times	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.5,1.8,2.5,3.3 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.05 ns
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm
minfmax	320 MHz

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ispClock 5500 Family

™

In-System Programmable Clock Generator

with Universal Fan-Out Buffer

February 2005

Data Sheet

Features

■

10MHz to 320MHz Input/Output Operation

Low Output to Output Skew (<50ps)

Low Jitter Peak-to-Peak(<70ps)

Up to 20 Programmable Fan-out Buffers

• Programmable output standards and individual

enable controls

- LVTTL, LVCMOS, HSTL, SSTL, LVDS,

LVPECL

• Programmable precision output impedance

- 40 to 70

Ω

in 5

Ω

increments

• Programmable slew rate

• Up to 10 banks with individual V

CCO

and GND

- 1.5V, 1.8V, 2.5V, 3.3V

■

Up to Five Clock Frequency Domains

■

Flexible Clock Reference Inputs

• Programmable input standards

- LVTTL, LVCMOS, SSTL, HSTL, LVDS,

LVPECL

• Clock A/B selection multiplexer

• Programmable precision termination

■

Four User-programmable Proﬁles Stored in

CMOS

Memory

• Supports both test and multiple operating

conﬁgurations

■

Fully Integrated High-Performance PLL

• Programmable lock detect

• Multiply and divide ratio controlled by

- Input divider (5 bits)

- Internal feedback divider (5 bits)

- Five output dividers (5 bits)

• Programmable On-chip Loop Filter

■

Full JTAG Boundary Scan Test In-System

Programming Support

■

Exceptional Power Supply Noise Immunity

■

Commercial (0 to 70°C) and Industrial

(-40 to 85°C) Temperature Ranges

■

100-pin and 48-pin TQFP Packages

■

Applications

• Circuit board common clock generation and

distribution

• PLL-based frequency generation

• High fan-out clock buffer

■

Precision Programmable Phase Adjustment

(Skew) Per Output

• 16 settings; minimum step size 195ps

- Locked to VCO frequency

• Up to +/- 12ns skew range

• Coarse and ﬁne adjustment modes

Product Family Block Diagram

LOCK DETECT

OUTPUT

DIVIDERS

BYPASS

MUX

FILTER

VCO

PLL CORE

OUTPUT

ROUTING

MATRIX

CLOCK OUTPUTS

PHASE/

FREQUENCY

DETECTOR

SKEW

CONTROL

OUTPUT

DRIVERS

REFERENCE

INPUTS

JTAG

INTERFACE

CMOS

MEMORY

Multiple Profile

Management Logic

INTERNAL FEEDBACK PATH

* Input Available only on ispClock 5520

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

clk5500_06.1

ISPPAC-CLK5520V-01TN100I Related Products

	ISPPAC-CLK5520V-01TN100I	ISPPAC-CLK5520V-01T100I	ISPPAC-CLK5520V-01T100C	ISPPAC-CLK5510V-01T48I	ISPPAC-CLK5510V-01TN48C
Description	Clock Drivers & Distribution PROGRAMMABLE CLOCK GENERATOR	Clock Drivers & Distribution PROGRAMMABLE CLOCK GENERATOR	Clock Drivers & Distribution PROGRAMMABLE CLOCK GENERATOR	Clock Drivers & Distribution PROGRAMMABLE CLOCK GENERATOR	Clock Drivers & Distribution PROGRAMMABLE CLOCK GENERATOR
Is it lead-free?	Lead free	Contains lead	Contains lead	Contains lead	Lead free
Is it Rohs certified?	conform to	incompatible	incompatible	incompatible	conform to
Maker	Lattice	Lattice	Lattice	Lattice	Lattice
Parts packaging code	QFP	QFP	QFP	QFP	QFP
package instruction	LFQFP, QFP100,.63SQ,20	TQFP-100	TQFP-100	LFQFP, QFP48,.35SQ,20	LFQFP, QFP48,.35SQ,20
Contacts	100	100	100	48	48
Reach Compliance Code	compliant	not_compliant	not_compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
series	5500	5500	5500	5500	5500
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL	DIFFERENTIAL
JESD-30 code	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G48	S-PQFP-G48
JESD-609 code	e3	e0	e0	e0	e3
length	14 mm	14 mm	14 mm	7 mm	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3	3	3	3	3
Number of functions	1	1	1	1	1
Number of terminals	100	100	100	48	48
Actual output times	20	20	20	10	10
Maximum operating temperature	85 °C	85 °C	70 °C	85 °C	70 °C
Minimum operating temperature	-40 °C	-40 °C	-	-40 °C	-
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20	QFP100,.63SQ,20	QFP100,.63SQ,20	QFP48,.35SQ,20	QFP48,.35SQ,20
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	240	240	240	260
power supply	1.5,1.8,2.5,3.3 V	1.5,1.8,2.5,3.3 V	1.5,1.8,2.5,3.3 V	1.5,1.8,2.5,3.3 V	1.5,1.8,2.5,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.05 ns	0.05 ns	0.05 ns	0.05 ns	0.05 ns
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	40	30	30	30	40
width	14 mm	14 mm	14 mm	7 mm	7 mm
minfmax	320 MHz	320 MHz	320 MHz	320 MHz	320 MHz

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