Data Sheet
FEATURES
500 kSPS, 2-Channel, Software-Selectable,
True Bipolar Input, 12-Bit Plus Sign ADC
AD7321
FUNCTIONAL BLOCK DIAGRAM
V
DD
REFIN/OUT
V
CC
12-bit plus sign SAR ADC
True bipolar input ranges
Software-selectable input ranges
±10 V, ±5 V, ±2.5 V, 0 V to +10 V
500 kSPS throughput rate
2 analog input channels with channel sequencer
Single-ended, true differential, and pseudo differential
analog input capability
High analog input impedance
Low power: 18 mW
Full power signal bandwidth: 22 MHz
Internal 2.5 V reference
High speed serial interface
Power-down modes
14-lead TSSOP package
iCMOS™
process technology
AD7321
2.5V
VREF
I/P
MUX
T/H
V
IN
0
V
IN
1
13-BIT
SUCCESSIVE
APPROXIMATION
ADC
DOUT
CHANNEL
SEQUENCER
CONTROL LOGIC
AND REGISTERS
SCLK
CS
DIN
V
DRIVE
AGND
V
SS
DGND
05399-001
Figure 1.
GENERAL DESCRIPTION
The
AD7321
1
is a 2-channel, 12-bit plus sign successive
approximation ADC designed on the
iCMOS
(industrial
CMOS) process.
iCMOS
is a process combining high voltage
silicon with submicron CMOS and complementary bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage parts could achieve.
Unlike analog ICs using conventional CMOS processes,
iCMOS
components can accept bipolar input signals while providing
increased performance, dramatically reduced power consumption,
and reduced package size.
The
AD7321
can accept true bipolar analog input signals. The
AD7321
has four software-selectable input ranges, ±10 V, ±5 V,
±2.5 V, and 0 V to +10 V. Each analog input channel is indepen-
dently programmed to one of the four input ranges. The analog
input channels on the
AD7321
are programmed to be single-ended,
true differential, or pseudo differential.
The ADC contains a 2.5 V internal reference. The
AD7321
also
allows for external reference operation. If a 3 V reference is applied
to the REFIN/OUT pin, the
AD7321
can accept a true bipolar
±12 V analog input. A minimum of ±12 V V
DD
and V
SS
supplies
are required for the ±12 V input range. The ADC has a high speed
serial interface that can operate at throughput rates up to 500 kSPS.
1
PRODUCT HIGHLIGHTS
1.
2.
The
AD7321
can accept true bipolar analog input signals,
±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.
The two analog inputs are configured as two single-ended
inputs, one true differential input pair, or one pseudo
differential input.
A 500 kSPS serial interface. SPI®-/QSPI™-/DSP-/
MICROWIRE™-compatible interface.
Low power, 18 mW, at a maximum throughput rate of
500 kSPS.
Channel sequencer.
Throughput
Rate
1000 kSPS
1000 kSPS
500 kSPS
1000 kSPS
500 kSPS
1000 kSPS
Number of
Channels
8
8
8
4
4
2
3.
4.
5.
Table 1. Similar Devices
Device
Number
AD7329
AD7328
AD7327
AD7324
AD7323
AD7322
Number of bits
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
Protected by U.S. Patent No. 6,731,232.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Document Feedback
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD7321
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 16
Circuit Information .................................................................... 16
Converter Operation .................................................................. 16
Analog Input Structure .............................................................. 17
Typical Connection Diagram ................................................... 19
Analog Input ............................................................................... 19
Driver Amplifier Choice ............................................................ 21
Registers ........................................................................................... 22
Addressing Registers .................................................................. 22
Data Sheet
Control Register ......................................................................... 23
Range Register ............................................................................ 25
Sequencer Operation ..................................................................... 26
Reference ..................................................................................... 27
V
DRIVE
............................................................................................ 27
Modes of Operation ....................................................................... 28
Normal Mode.............................................................................. 28
Full Shutdown Mode.................................................................. 28
Autoshutdown Mode ................................................................. 29
Autostandby Mode ..................................................................... 29
Power vs. Throughput Rate ....................................................... 30
Serial Interface ................................................................................ 31
Microprocessor Interfacing ........................................................... 32
AD7321 to ADSP-21xx .............................................................. 32
AD7321 to ADSP-BF53x ........................................................... 32
Application Hints ........................................................................... 33
Layout and Grounding .............................................................. 33
Power Supply Configuration .................................................... 33
Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
12/13—Rev. A to Rev. B
Changes to Circuit Information Section and Table 6 ................ 16
Changes to Addressing Registers Section.................................... 22
Changes to Power Supply Configuration Section ...................... 33
10/09—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................ 4
Changes to Figure 53 ...................................................................... 33
Changes to Power Supply Configuration Section ...................... 33
Changes to Table 16 ........................................................................ 33
Changes to Outline Dimensions................................................... 34
Changes to Ordering Guide .......................................................... 34
1/06—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet
SPECIFICATIONS
AD7321
V
DD
= 12 V to 16.5 V, V
SS
= −12 V to −16.5 V, V
CC
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, V
REF
= 2.5 V to 3.0 V internal/external,
f
SCLK
= 10 MHz, f
S
= 500 kSPS, T
A
= T
MAX
to T
MIN
, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
2
1
Min
76
75.5
72.5
72
B Version
Typ
Max
Unit
dB
dB
dB
dB
dB
Signal-to-Noise + Distortion
(SINAD)
2
75
74
76
72
72.5
Test Conditions/Comments
F
IN
= 50 kHz sine wave
Differential mode, V
CC
= 4.75 V to 5.25 V
Differential mode, V
CC
< 4.75 V
Single-ended/pseudo differential mode: ±10 V,
±2.5 V and ±5 V ranges, V
CC
= 4.75 V to 5.25 V
Single-ended/pseudo differential mode: 0 V to
10 V V
CC
= 4.75 V to 5.25 V and all ranges at V
CC
<
4.75 V
Differential mode: ±2.5 V and ±5 V ranges
Differential mode: 0 V to 10 V
Differential mode: ±10 V range
Single-ended/pseudo differential mode: ±2.5 V
and ±5 V ranges
Single-ended/pseudo differential mode: 0 V to
+10 V and ±10 V ranges
Differential mode: ±2.5 V and ±5 V ranges
Differential mode: 0 V to 10 V ranges
Differential mode: ±10 V range
Single-ended/pseudo differential mode:
±5 V range
Single-ended/pseudo differential mode:
±2.5 V range
Single-ended/pseudo differential mode: 0 V to
+10 V and ±10 V ranges
Differential mode: ±2.5 V and ±5 V ranges
Differential mode: 0 V to 10 V ranges
Differential mode: ±10 V ranges
Single-ended/pseudo differential mode:
±5 V range
Single-ended/pseudo differential mode:
±2.5 V range
Single-ended/pseudo differential mode: 0 V to
+10 V and ±10 V ranges
fa = 50 kHz, fb = 30 kHz
dB
dB
dB
−80
−79
dB
dB
dB
dB
dB
dB
−81
−80
dB
dB
dB
dB
Total Harmonic Distortion
(THD)
2
−82
−77
−79
−80
Peak Harmonic or Spurious
Noise (SFDR)
2
−82
−78
−80
−79
Intermodulation Distortion
(IMD)
2
Second-Order Terms
Third-Order Terms
Aperture Delay
3
Aperture Jitter
3
Common-Mode Rejection
(CMRR)
2
Channel-to-Channel
Isolation
2
Full Power Bandwidth
dB
−88
−90
7
50
−79
−72
22
5
dB
dB
ns
ps
dB
dB
MHz
MHz
Up to 100 kHz ripple frequency: see Figure 17
F
IN
on unselected channels up to 100 kHz: see
Figure 14
At 3 dB
At 0.1 dB
Rev. B | Page 3 of 36
AD7321
Parameter
DC ACCURACY
4
1
Data Sheet
Min
B Version
Typ
Max
Unit
Test Conditions/Comments
Differential mode LSB = FSR/8192
Single-ended/pseudo differential mode
LSB = FSR/4096, unless otherwise noted
Differential mode
Single-ended/pseudo differential mode
Differential mode; V
CC
= 3 V to 5.25 V, typ for
V
CC
= 2.7 V
Single-ended/pseudo differential mode, V
CC
=
3 V to 5.25 V, typ for V
CC
= 2.7 V
Single ended/pseudo differential mode
LSB = FSR/8192
Differential mode; guaranteed no missing
codes to 13 bits
Single-ended mode; guaranteed no missing
codes to 12 bits
Single ended/pseudo differential mode,
LSB = FSR/8192
Differential mode LSB = FSR/8192
Equates to −7/+10 LSBs
Equates to ±0.5 LSBs
Equates to ±14 LSBs
Equates to ±0.5 LSBs
Equates to ±7 LSBs
Equates to ±0.5 LSBs
Equates to ±7.5 LSBs
Equates to ±0.5 LSBs
Equates to ±6 LSBs
Equates to ±0.5 LSBs
Single-ended/pseudo differential mode
LSB = FSR/4096
Equates to −4/+9 LSBs
Equates to ±0.6 LSBs
Equates to ±8 LSBs
Equates to ±0.5 LSBs
Equates to ±4 LSBs
Equates to ±0.5 LSBs
Equates to ±8.5LSBs
Equates to ±0.5 LSBs
Equates to ±4 LSBs
Equates to ±0.5 LSBs
Resolution
No Missing Codes
13
12-bit plus
sign (13 bits)
11-bit plus
sign (12 bits)
±1.1
±1
−0.7/+1.2
Bits
Bits
Bits
LSB
LSB
LSB
−0.9/+1.2
±0.9
−0.7/+1
LSB
LSB
LSB
Integral Nonlinearity
2
Differential Nonlinearity
2
Offset Error
2, 5
Offset Error Match
2,5
Gain Error
2, 5
Gain Error Match
2, 5
Positive Full-Scale Error
2, 6
Positive Full-Scale Error
Match
2, 6
Bipolar Zero Error
2, 6
Bipolar Zero Error Match
2, 6
Negative Full-Scale Error
2, 6
Negative Full-Scale Error
Match
2, 6
−0.085/+0.122
±0.006
±0.171
±0.006
±0.085
±0.006
±0.092
±0.006
±0.073
±0.006
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
Offset Error
2, 5
Offset Error Match
2, 5
Gain Error
2, 5
Gain Error Match
2, 5
Positive Full-Scale Error
2, 6
Positive Full-Scale Error
Match
2, 6
Bipolar Zero Error
2, 6
Bipolar Zero Error Match
2, 6
Negative Full-Scale Error
2, 6
Negative Full-Scale Error
Match
2, 6
−0.098/+0.22
±0.015
±0.195
±0.012
±0.098
±0.012
±0.208
±0.012
±0.098
±0.012
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
Rev. B | Page 4 of 36
Data Sheet
Parameter
ANALOG INPUT
Input Voltage Ranges
(Programmed via Range
Register)
1
AD7321
Min
B Version
Typ
Max
Unit
Test Conditions/Comments
Reference = 2.5 V; see Table 6
V
DD
= 10 V min, V
SS
= −10 V min, V
CC
= 2.7 V to
5.25 V
V
DD
= 5 V min, V
SS
= −5 V min, V
CC
= 2.7 V to 5.25 V
V
DD
= 5 V min, V
SS
= −5 V min, V
CC
= 2.7 V to 5.25 V
V
DD
= 10 V min, V
SS
= AGND min, V
CC
= 2.7 V to
5.25 V
V
DD
= 16.5 V, V
SS
= −16.5 V, V
CC
= 5 V; see Figure 40
and Figure 41
Reference = 2.5 V; range = ±10 V
Reference = 2.5 V; range = ±5 V
Reference = 2.5 V; range = ±2.5 V
Reference = 2.5 V; range = 0 V to +10 V
V
IN
= V
DD
or V
SS
Per input channel, V
IN
= V
DD
or V
SS
When in track, ±10 V range
When in track, ±5 V and 0 V to +10 V ranges
When in track, ±2.5 V range
When in hold, all ranges
±10
±5
±2.5
0 to 10
V
V
V
V
Pseudo Differential V
IN
(−)
Input Range
±3.5
±6
±5
+3/−5
DC Leakage Current
Input Capacitance
3
±80
3
13.5
16.5
21.5
3
2.5
10
2.5
±5
±10
25
3
7
3
±1
V
V
V
V
nA
nA
pF
pF
pF
pF
V
µA
pF
V
mV
mV
ppm/°C
ppm/°C
Ω
REFERENCE INPUT/OUTPUT
Input Voltage Range
Input DC Leakage Current
Input Capacitance
Reference Output Voltage
Reference Output Voltage
Error at 25°C
Reference Output Voltage
T
MIN
to T
MAX
Reference Temperature
Coefficient
Reference Output
Impedance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage
Current
Floating-State Output
Capacitance
3
Output Coding
2.4
0.8
0.4
±1
10
V
DRIVE
− 0.2 V
0.4
±1
5
Straight natural binary
Twos complement
V
V
V
µA
pF
V
V
µA
pF
V
CC
= 4.75 V to 5.25 V
V
CC
= 2.7 to 3.6 V
V
IN
= 0 V or V
DRIVE
I
SOURCE
= 200 µA
I
SINK
= 200 µA
Coding bit set to 1 in control register
Coding bit set to 0 in control register
Rev. B | Page 5 of 36
京公网安备 11010802033920号
EEWORLD
