ORCA
®
ORT8850
Field-Programmable System Chip (FPSC)
Eight-Channel x 850 Mbits/s Backplane Transceiver
February 2008
Data Sheet
Introduction
Field Programmable System-on-a-Chip (FPSCs) bring a whole new dimension to programmable logic: Field Pro-
grammable Gate Array (FPGA) logic and an embedded system solution on a single device. Lattice has developed
a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-
speed serial backplane data transfer. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC)
architecture, the ORT8850 family is made up of backplane transceivers (SERDES) containing eight channels, each
operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used). This is combined with a full-duplex
synchronous interface, with built-in Clock and Data Recovery (CDR) in standard-cell logic, along with over 600K
usable FPGA system gates (ORT8850H). With the addition of protocol and access logic such as protocol-indepen-
dent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET (PoS) interfaces, and framers for
HDLC for Internet Protocol (IP), designers can build a configurable interface retaining proven backplane
driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within
a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge
using our PCI soft core.
The ORT8850 family offers a clockless High-Speed Interface for inter-device communication on a board or across
a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design
clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the
backplane transceiver as a network termination device. The backplane transceiver offers SONET scram-
bling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus
the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all
SONET functionality is hidden from the user and no prior networking knowledge is required.
Table 1. ORCA ORT8850 Family – Available FPGA Logic (equivalent to OR4E02 and OR4E06 respectively)
PFU
Columns
24
44
FPGA Max
Total PFUs User I/Os
624
2,024
278
297
EBR
Blocks
8
16
EBR Bits
(K)
74
148
FPGA
System
Gates (K)
201 - 397
471 - 899
Device
ORT8850L
ORT8850H
PFU Rows
26
46
LUTs
4,992
16,192
Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate
ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40%
EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage
and 6 PLLs.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
1
ort8850_11.1
Lattice Semiconductor
ORCA ORT8850 Data Sheet
Package Thermal Characteristics Summary............ 100
qJA .............................................................. 100
YJC ............................................................. 100
qJC.............................................................. 100
qJB .............................................................. 100
FPSC Maximum Junction Temperature ...... 101
Package Thermal Characteristics ............... 101
Heat Sink Information.................................. 101
Package Coplanarity ................................... 101
Package Parasitics................................................... 102
Package Outline Diagrams ...................................... 102
Terms and Definitions ................................. 102
Package Outline Drawings.......................... 103
Ordering Information ................................................ 104
Revision History ....................................................... 105
Table of Contents
Introduction .................................................................. 1
Table of Contents......................................................... 2
Features ....................................................................... 3
Embedded Core Features............................... 3
FPGA Features ............................................... 4
Programmable Logic System Features........... 5
Description ................................................................... 6
What is an FPSC?........................................... 6
FPSC Overview............................................... 6
ispLEVER Development System..................... 7
FPSC Design Kit ............................................. 7
FPGA Logic Overview..................................... 8
System-Level Features ................................... 9
Configuration................................................. 10
Additional Information ................................... 10
ORT8850 Overview ................................................... 11
Embedded Core Overview ............................ 11
SONET Logic Blocks - Overview .................. 12
System Considerations for Reference Clock
Distribution.............................................. 15
SONET Bypass Mode ................................... 16
STM Macrocells - Overview .......................... 17
HSI Macrocell - Overview.............................. 19
Supervisory and Test Support Features - Over-
view ........................................................ 19
Protection Switching - Overview ................... 21
FPSC Configuration - Overview .................... 22
Backplane Transceiver Core Detailed Description .... 25
SONET Logic Blocks, Detailed Description .. 25
Receive Path Logic ....................................... 34
FPGA/Embedded Core Interface Signals .................. 47
Clock and Data Timing at the FPGA/Embedded
Core Interface - SONET Block ............... 49
Powerdown Mode ......................................... 56
Protection Switching...................................... 56
Memory Map .............................................................. 57
Registers Access and General Description... 57
Electrical Characteristics............................................ 69
Absolute Maximum Ratings .......................... 69
Recommended Operating Conditions ........................ 69
Power Supply Decoupling LC Circuit ............ 70
HSI Electrical and Timing Characteristics ..... 71
Embedded Core LVDS I/O............................ 73
Pin Information ........................................................... 77
Package Pinouts ........................................................ 82
2
Lattice Semiconductor
ORCA ORT8850 Data Sheet
Features
Embedded Core Features
• Implemented in an
ORCA
Series 4 FPGA.
• Allows a wide range of high-speed backplane applications, including SONET transport and termination.
• No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz—106 MHz clock,
and a frame pulse.
• High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external
clocks.
• Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of 6.8
Gbits/s (full duplex).
• HSI function uses Lattice’s 850 Mbits/s serial interface core. Rates from 126 Mbits/s to 850 Mbits/s are sup-
ported.
• LVDS I/Os compliant with
EIA
®
-644 support hot insertion. All embedded LVDS I/Os include both input and output
on-board termination to allow long-haul driving of backplanes.
• Low-power 1.5 V HSI core.
• Low-power LVDS buffers.
• Programmable STS-3, and STS-12 framing.
• Independent STS-3, and STS-12 data streams per quad channels.
• 8:1 data multiplexing/demultiplexing for 106.25 MHz byte-wide data processing in FPGA logic.
• On-chip, Phase-Lock Loop (PLL) clock meets (type B) jitter tolerance specification of ITU-T recommendation
G.958.
• Powerdown option of HSI receiver on a per-channel basis.
• HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state.
• Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above
rates.
• In-band management and configuration through transport overhead extraction/insertion.
• Supports transparent modes where either the only insertion is A1/A2 framing bytes, or no bytes are inserted.
• Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks.
• Built-in boundry scan (
IEEE
®
1149.1 JTAG).
• FIFOs align incoming data across all eight channels (two groups of four channels or four groups of two channels)
for both SONET scrambling. Optional ability to bypass alignment FIFOs.
• 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection
switching applications. STS-192 and above rates are supported through multiple devices.
•
ORCA
FPGA soft intellectual property core support for a variety of applications.
• Programmable Synchronous Transport Module (STM) pointer mover bypass mode.
• Programmable STM framer bypass mode.
• Programmable Clock and Data Recovery (CDR) bypass mode (clocked LVDS High-Speed Interface).
• Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channels
with redundancy on a single device.
3
Lattice Semiconductor
FPGA Features
ORCA ORT8850 Data Sheet
• High-performance platform design:
– 0.16 µm 7-level metal technology.
– Internal performance of >250 MHz.
– Over 600K FPGA system gates (ORT8850H).
– Meets multiple I/O interface standards.
– 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
• Traditional I/O selections:
– LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os.
– Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.
– Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA
sink/3 mA source.
– Two slew rates supported (fast and slew-limited).
– Fast-capture input latch and input flip-flop/latch for reduced input setup time and zero hold time.
– Fast open-drain drive capability.
– Capability to register 3-state enable signal.
– Off-chip clock drive capability.
– Two-input function generator in output path.
• New programmable high-speed I/O:
– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, LVPECL.
– LVDS include optional on-chip termination resistor per I/O and on-chip reference generation.
• New capability to (de)multiplex I/O signals:
– New Double-Data Rate (DDR) on both input and output at rates up to 350 MHz (700 Mbits/s effective rate).
– New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
• Enhanced twin-quad Programmable Function Unit (PFU):
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act indepen-
dently, plus one extra for arithmetic operations.
– New register control in each PFU has two independent programmable clocks, clock enables, local
SET/RESET, and data selects.
– New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4
→
1 MUX, new 8
→
1 MUX,
and ripple mode arithmetic functions in the same PFU.
– 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in
only eight PFUs) using the SLIC decoders as bank drivers.
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast
internal routing, which reduces routing congestion and improves speed.
– Flexible fast access to PFU inputs from routing.
– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func-
tions, with the option to register the PFU carry-out.
• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over
previous architectures.
• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
faster routing times with predictable and efficient performance.
• SLIC provides eight 3-State Buffers, up to 10-bit decoder, and
PAL
®
-like AND-OR-INVERT (AOI) in each pro-
grammable logic cell.
• Improved built-in clock management with dual-output Programmable Phase-Locked Loops (PPLLs) provide opti-
mum clock modification and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Mul-
tiplication of the input frequency up to 64x, and division of the input frequency down to 1/64x possible.
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
• New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane
enables. Each embedded RAM block can be configured as:
– One—512 x 18 (quad-port, two read/two write) with optional built-in arbitration.
– One—256 x 36 (dual-port, one read/one write).
– One—1K x 9 (dual-port, one read/one write).
– Two—512 x 9 (dual-port, one read/one write for each).
– Two RAM with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).
– Supports joining of RAM blocks.
– Two 16 x 8-bit Content Addressable Memory (CAM) support.
– FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9.
– Constant multiply (8 x 16 or 16 x 8).
– Dual variable multiply (8 x 8).
• Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),
embedded RAM blocks, and embedded backplane transceiver blocks with 100 MHz bus performance. Included
are built-in system registers that act as the control and status center for the device.
• Built-in testability:
– Full boundary scan (
IEEE
1149.1 and Draft 1149.2 JTAG).
– Programming and readback through boundary scan port compliant to
IEEE
Draft 1532:D1.7.
– TS_ALL testability function to 3-state all I/O pins.
– New temperature-sensing diode.
• Cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This
feature also supports compliance with many setup/hold and clock to out I/O specifications and may provide
reduced ground bounce for output buses by allowing flexible delays of switching output buffers.
Programmable Logic System Features
• PCI local bus compliant for FPGA I/Os.
• Improved
PowerPC/Power QUICC MPC860
and
PowerPC
II
MPC8260
high-speed synchronous MicroProcessor
Interface can be used for configuration, readback, device control, and device status, as well as for a general-pur-
pose interface to the FPGA logic, RAMs, and embedded backplane transceiver blocks. Glueless interface to syn-
chronous
PowerPC
processors with user-configurable address space provided.
• New embedded
AMBA
™
specification 2.0 AHB system bus (
ARM
®
processor) facilitates communication among
the MicroProcessor Interface, configuration logic, embedded block RAM, FPGA logic, and backplane transceiver
logic.
• New network PLLs meet ITU-T G.811 specifications and provide clock conditioning for DS-1/E-1 and STS-
3/STM-1 applications.
• Variable size bused readback of configuration data capability with the built-in MicroProcessor Interface and sys-
tem bus.
• Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
• New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200
ps for OR4E04).
• New local clock routing structures allow creation of localized clock trees.
• Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved
setup/hold and clock-to-out performance.
• New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest high-
speed memory interfaces.
• New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal
logic.
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