Features
•
High-performance, Low-power 32-bit Atmel
®
AVR
®
Microcontroller
– Compact Single-cycle RISC Instruction Set Including DSP Instructions
– Read-modify-write Instructions and Atomic Bit Manipulation
– Performance
• Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State)
• Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State)
– Memory Protection Unit (MPU)
• Secure Access Unit (SAU) providing User-defined Peripheral Protection
picoPower
®
Technology for Ultra-low Power Consumption
Multi-hierarchy Bus System
– High-performance Data Transfers on Separate Buses for Increased Performance
– 12 Peripheral DMA Channels improve Speed for Peripheral Communication
Internal High-speed Flash
– 256Kbytes, 128Kbytes, and 64Kbytes Versions
– Single-cycle Access up to 25MHz
– FlashVault Technology Allows Pre-programmed Secure Library Support for End
User Applications
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User-defined Configuration Area
Internal High-speed SRAM, Single-cycle Access at Full Speed
– 32Kbytes (256Kbytes and 128Kbytes Flash) and 16Kbytes (64Kbytes Flash)
Interrupt Controller (INTC)
– Autovectored Low-latency Interrupt Service with Programmable Priority
External Interrupt Controller (EIC)
Peripheral Event System for Direct Peripheral to Peripheral Communication
System Functions
– Power and Clock Manager
– SleepWalking Power Saving Control
– Internal System RC Oscillator (RCSYS)
– 32 KHz Oscillator
– Multipurpose Oscillator, Phase Locked Loop (PLL), and Digital Frequency Locked
Loop (DFLL)
Windowed Watchdog Timer (WDT)
Asynchronous Timer (AST) with Real-time Clock Capability
– Counter or Calendar Mode Supported
Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
Universal Serial Bus (USBC)
– Full Speed and Low Speed USB Device Support
– Multi-packet Ping-pong Mode
Six 16-bit Timer/Counter (TC) Channels
– External Clock Inputs, PWM, Capture, and Various Counting Capabilities
36 PWM Channels (PWMA)
– 12-bit PWM with a Source Clock up to 150MHz
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Independent Baudrate Generator, Support for SPI
– Support for Hardware Handshaking
•
•
•
32-bit Atmel
AVR
Microcontroller
ATUC256L3U
ATUC128L3U
ATUC64L3U
ATUC256L4U
ATUC128L4U
ATUC64L4U
Summary
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32142DS–06/2013
ATUC64/128/256L3/4U
•
One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals
•
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•
– Up to 15 SPI Slaves can be Addressed
Two Master and Two Slave Two-wire Interfaces (TWI), 400kbit/s I
2
C-compatible
One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution
– Internal Temperature Sensor
Eight Analog Comparators (AC) with Optional Window Detection
Capacitive Touch (CAT) Module
– Hardware-assisted Atmel
®
AVR
®
QTouch
®
and Atmel
®
AVR
®
QMatrix Touch Acquisition
– Supports QTouch and QMatrix Capture from Capacitive Touch Sensors
QTouch Library Support
– Capacitive Touch Buttons, Sliders, and Wheels
– QTouch and QMatrix Acquisition
Audio Bitstream DAC (ABDACB) Suitable for Stereo Audio
Inter-IC Sound (IISC) Controller
– Compliant with Inter-IC Sound (I
2
S) Specification
On-chip Non-intrusive Debug System
– Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace
– aWire Single-pin Programming Trace and Debug Interface, Muxed with Reset Pin
– NanoTrace Provides Trace Capabilities through JTAG or aWire Interface
64-pin TQFP/QFN (51 GPIO Pins), 48-pin TQFP/QFN/TLLGA (36 GPIO Pins)
Six High-drive I/O Pins (64-pin Packages), Four High-drive I/O Pins (48-pin Packages)
Single 1.62-3.6V Power Supply
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2
32142DS–06/2013
ATUC64/128/256L3/4U
1. Description
The Atmel
®
AVR
®
ATUC64/128/256L3/4U is a complete system-on-chip microcontroller based
on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-
performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applica-
tions, with particular emphasis on low power consumption, high code density, and high
performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern and real-time operating systems. The Secure Access Unit (SAU) is
used together with the MPU to provide the required security and integrity.
Higher computation capability is achieved using a rich set of DSP instructions.
The ATUC64/128/256L3/4U embeds state-of-the-art picoPower technology for ultra-low power
consumption. Combined power control techniques are used to bring active current consumption
down to 174µA/MHz, and leakage down to 220nA while still retaining a bank of backup regis-
ters. The device allows a wide range of trade-offs between functionality and power consumption,
giving the user the ability to reach the lowest possible power consumption with the feature set
required for the application.
The Peripheral Direct Memory Access (DMA) controller enables data transfers between periph-
erals and memories without processor involvement. The Peripheral DMA controller drastically
reduces processing overhead when transferring continuous and large data streams.
The ATUC64/128/256L3/4U incorporates on-chip Flash and SRAM memories for secure and
fast access. The FlashVault technology allows secure libraries to be programmed into the
device. The secure libraries can be executed while the CPU is in Secure State, but not read by
non-secure software in the device. The device can thus be shipped to end customers, who will
be able to program their own code into the device to access the secure libraries, but without risk
of compromising the proprietary secure code.
The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each
external interrupt has its own interrupt request and can be individually masked.
The Peripheral Event System allows peripherals to receive, react to, and send peripheral events
without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low
power sleep modes.
The Power Manager (PM) improves design flexibility and security. The Power Manager supports
SleepWalking functionality, by which a module can be selectively activated based on peripheral
events, even in sleep modes where the module clock is stopped. Power monitoring is supported
by on-chip Power-on Reset (POR), Brown-out Detector (BOD), and Supply Monitor (SM). The
device features several oscillators, such as Phase Locked Loop (PLL), Digital Frequency
Locked Loop (DFLL), Oscillator 0 (OSC0), and system RC oscillator (RCSYS). Either of these
oscillators can be used as source for the system clock. The DFLL is a programmable internal
oscillator from 20 to 150MHz. It can be tuned to a high accuracy if an accurate reference clock is
running, e.g. the 32KHz crystal oscillator.
The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the soft-
ware. This allows the device to recover from a condition that has caused the system to be
unstable.
The Asynchronous Timer (AST) combined with the 32KHz crystal oscillator supports powerful
real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in
counter or calendar mode.
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32142DS–06/2013
ATUC64/128/256L3/4U
The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it
to a known reference clock.
The Full-speed USB 2.0 device interface (USBC) supports several USB classes at the same
time, thanks to the rich end-point configuration.
The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-
pendently programmed to perform frequency measurement, event counting, interval
measurement, pulse generation, delay timing, and pulse width modulation.
The Pulse Width Modulation controller (PWMA) provides 12-bit PWM channels which can be
synchronized and controlled from a common timer. 36 PWM channels are available, enabling
applications that require multiple PWM outputs, such as LCD backlight control. The PWM chan-
nels can operate independently, with duty cycles set individually, or in interlinked mode, with
multiple channels changed at the same time.
The ATUC64/128/256L3/4U also features many communication interfaces, like USART, SPI,
and TWI, for communication intensive applications. The USART supports different communica-
tion modes, like SPI Mode and LIN Mode.
A general purpose 8-channel ADC is provided, as well as eight analog comparators (AC). The
ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering
up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel.
The analog comparators can be paired to detect when the sensing voltage is within or outside
the defined reference window.
The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using
the QTouch technology. Capacitive touch sensors use no external mechanical components,
unlike normal push buttons, and therefore demand less maintenance in the user application.
The CAT module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced.
All touch sensors can be configured to operate autonomously without software interaction,
allowing wakeup from sleep modes when activated.
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and includes fully debounced reporting of touch keys as well as Adjacent Key
Suppression
®
(AKS
®
) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications.
The Audio Bitstream DAC (ABDACB) converts a 16-bit sample value to a digital bitstream with
an average value proportional to the sample value. Two channels are supported, making the
ABDAC particularly suitable for stereo audio.
The Inter-IC Sound Controller (IISC) provides a 5-bit wide, bidirectional, synchronous, digital
audio link with external audio devices. The controller is compliant with the Inter-IC Sound (I2S)
bus specification.
The ATUC64/128/256L3/4U integrates a class 2+ Nexus 2.0 On-chip Debug (OCD) System,
with non-intrusive real-time trace and full-speed read/write memory access, in addition to basic
runtime control. The NanoTrace interface enables trace feature for aWire- or JTAG-based
debuggers. The single-pin aWire interface allows all features available through the JTAG inter-
face to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or
peripherals.
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32142DS–06/2013
ATUC64/128/256L3/4U
2. Overview
2.1
Block Diagram
Figure 2-1.
Block Diagram
AVR32UC CPU
NEXUS
CLASS 2+
OCD
MEMORY INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
EVTO_N
TCK
TDO
TDI
TMS
DATAOUT
RESET_N
LOCAL BUS
INTERFACE
LOCAL BUS
JTAG
INTERFACE
aWire
MEMORY PROTECTION UNIT
INSTR
INTERFACE
DATA
INTERFACE
32/16 KB
SRAM
M
SAU
S/M
M
M
S
FLASH
CONTROLLER
HIGH SPEED
BUS MATRIX
DP
S
256/128/64
KB
FLASH
USB 2.0
Interface
8EP
S
S
CONFIGURATION
DM
S
REGISTERS BUS
M
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
PERIPHERAL
DMA
CONTROLLER
GENERALPURPOSE I/Os
PA
PB
CLOCK
CONTROLLER
SLEEP
CONTROLLER
RESET
CONTROLLER
DMA
POWER MANAGER
CAPACITIVE TOUCH
MODULE
DIS
VDIVEN
CSA[16:0]
CSB[16:0]
SMP
SYNC
USART0
USART1
USART2
USART3
RXD
TXD
CLK
RTS, CTS
SCK
DMA
DMA
NPCS[3..0]
RCSYS
DMA
RC32OUT
RC32K
RC120M
SYSTEM CONTROL
INTERFACE
TWCK
TWI MASTER 0
TWI MASTER 1
GENERAL PURPOSE I/Os
GCLK_IN[2..0]
GCLK[9..0]
SPI
MISO, MOSI
TWD
TWALM
TWCK
PA
PB
XIN32
XOUT32
XIN0
XOUT0
OSC32K
OSC0
DFLL
PLL
TWI SLAVE 0
TWI SLAVE 1
DMA
TWD
TWALM
ADP[1..0]
8-CHANNEL ADC
INTERFACE
DMA
TRIGGER
AD[8..0]
ADVREFP
ISCK
IWS
ISDI
ISDO
IMCK
CLK
INTERRUPT
CONTROLLER
EXTINT[5..1]
NMI
INTER-IC SOUND
CONTROLLER
DMA
DMA
EXTERNAL INTERRUPT
CONTROLLER
AUDIO BITSTREAM
DAC
DAC0, DAC1
DACN0, DACN1
PWMA[35..0]
PWM CONTROLLER
AC INTERFACE
ASYNCHRONOUS
TIMER
WATCHDOG
TIMER
FREQUENCY METER
GLUE LOGIC
CONTROLLER
ACBP[3..0]
ACBN[3..0]
ACAP[3..0]
ACAN[3..0]
ACREFN
OUT[1..0]
IN[7..0]
TIMER/COUNTER 0
TIMER/COUNTER 1
A[2..0]
B[2..0]
CLK[2..0]
5
32142DS–06/2013
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