NCP1271
Soft-Skipt Mode Standby
PWM Controller with
Adjustable Skip Level and
External Latch
The NCP1271 represents a new, pin to pin compatible, generation
of the successful 7−pin current mode NCP12XX product series. The
controller allows for excellent stand by power consumption by use of
its adjustable Soft−Skip mode and integrated high voltage startup
FET. This proprietary Soft−Skip also dramatically reduces the risk of
acoustic noise. This allows the use of inexpensive transformers and
capacitors in the clamping network. Internal frequency jittering,
ramp compensation, timer−based fault detection and a latch input
make this controller an excellent candidate for converters where
ruggedness and component cost are the key constraints.
Features
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MARKING
DIAGRAMS
8
SOIC−7
D SUFFIX
CASE 751U
1271x
ALYWG
G
1
•
Fixed−Frequency Current−Mode Operation with Ramp
•
•
•
•
•
•
•
•
•
•
•
PDIP−7 VHVIC
P SUFFIX
CASE 626B
8
1
x
1
1271Pxxx
AWL
YYWWG
Compensation and Skip Cycle in Standby Condition
Timer−Based Fault Protection for Improved Overload Detection
“Soft−Skip Mode” Technique for Optimal Noise Control in Standby
Internal High−Voltage Startup Current Source for Lossless Startup
"5%
Current Limit Accuracy over the Full Temperature Range
Adjustable Skip Level
Internal Latch for Easy Implementation of Overvoltage and
Overtemperature Protection
Frequency Jittering for Softened EMI Signature
+500 mA/−800 mA Peak Current Drive Capability
Sub−100 mW Standby Power can be Achieved
Pin−to−Pin Compatible with the Existing NCP120X Series
This is a Pb−Free Device
= A or B
A= 65 kHz
B= 100 kHz
xxx
= Device Code: 65, 100
A
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G
or G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
Skip/latch
FB
CS
GND
1
2
3
4
(Top View)
6
5
8
HV
V
CC
Drv
Typical Applications
•
AC−DC Adapters for Notebooks, LCD Monitors
•
Offline Battery Chargers
•
Consumer Electronic Appliances STB, DVD, DVDR
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2009
September, 2009
−
Rev. 6
1
Publication Order Number:
NCP1271/D
NCP1271
+
AC
Input
EMI
Filter
Output
Voltage
−
latch input*
*
Optional
R
skip
skip/latch HV
FB
Vcc
CS
Drv
Gnd
NCP1271
R*
ramp
Figure 1. Typical Application Circuit
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2
NCP1271
MAXIMUM RATINGS
(Notes 1 and 2)
Rating
V
CC
Pin (Pin 6)
Maximum Voltage Range
Maximum Current
Skip/Latch, FB, CS Pin (Pins 1−3)
Maximum Voltage Range
Maximum Current
Drv Pin (Pin 5)
Maximum Voltage Range
Maximum Current
HV Pin (Pin 8)
Maximum Voltage Range
Maximum Current
Power Dissipation and Thermal Characteristics
Thermal Resistance, Junction−to−Air, PDIP−7, Low Conductivity PCB (Note 3)
Thermal Resistance, Junction−to−Lead, PDIP−7, Low Conductivity PCB
Thermal Resistance, Junction−to−Air, PDIP−7, High Conductivity PCB (Note 4)
Thermal Resistance, Junction−to−Lead, PDIP−7, High Conductivity PCB
Thermal Resistance, Junction−to−Air, SO−7, Low Conductivity PCB (Note 3)
Thermal Resistance, Junction−to−Lead, SO−7, Low Conductivity PCB
Thermal Resistance, Junction−to−Air, SO−7, High Conductivity PCB (Note 4)
Thermal Resistance, Junction−to−Lead, SO−7, High Conductivity PCB
Operating Junction Temperature Range
Maximum Storage Temperature Range
ESD Protection
Human Body Model ESD Pins 1−6
Human Body Model ESD Pin 8
Machine Model ESD Pins 1−4, 8
Machine Model ESD Pins 5, 6
Charged Device Model ESD
Symbol
V
max
I
max
V
max
I
max
V
max
I
max
V
max
I
max
R
qJA
R
qJL
R
qJA
R
qJL
R
qJA
R
qJL
R
qJA
R
qJL
T
J
T
stg
HBM
HBM
MM
MM
CDM
Value
−0.3
to +20
100
−0.3
to +10
100
−0.3
to +20
−800
to +500
−0.3
to +500
100
142
57
120
56
177
75
136
69
−40
to +150
−60
to +150
2000
700
200
150
1000
Unit
V
mA
V
mA
V
mA
V
mA
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
°C
V
V
V
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. ESD protection per JEDEC JESD22−A114−F for HBM, per JEDEC JESD22−A115−A for MM, and per JEDEC JESD22−C101D for CDM.
This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
2. Guaranteed by design, not tested.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm
2
of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm
2
of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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3
NCP1271
Skip/ latch
1
R
skip
I
skip
8V
−
+
13 us filter
V
skip
V
FB
2.85 V
TLD
−
+
disable
soft
skip
skip
+
−
soft−skip
S
soft
start
Q
R
S
R
Q
4.1 mA when Vcc > 0.6 V
0.2 mA when Vcc < 0.6 V
turn off
12.6/
5.8 V
−
+
UVLO
latch−off, reset
when Vcc < 4V
8
HV
10V
V
skip
= R
skip
* I
skip
or
V
skip
= 1.2 V when pin 1 is opened
4.8 V
FB
2
75.3k
1/3
10V
V
FB
/ 3
V
FB
16.7k
0
V
ss
Soft start/ soft−skip
(1V max)
management
4 ms/ 300 us
−
+
130ms
delay
&
1
V
PWM
PWM
−
+
CS
3
R
ramp
V
CS
10V
short
circuit
fault
double
hiccup
B2
Counter
9.1 V
−
+
20V
V
CC
6
180 ns
LEB
100uA
0
jittered ramp
current source
&
turn on internal bias
V
CC
OR
R
CS
4
Gnd
1
0
Drv
7.5% Jittering
65, 100 kHz
Oscillator
R
Q
S
Max duty
= 80%
driver:
+500 mA
/
−800
mA
5
Figure 2. Functional Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
1
2
Symbol
Skip/latch
FB
Function
Skip Adjust or
Latchoff
Feedback
Description
A resistor to ground provides the adjustable standby skip level. Additionally, if this pin is
pulled higher than 8.0 V (typical), the controller latches off the drive.
An optocoupler collector pulls this pin low during regulation. If this voltage is less than
the Skip pin voltage, then the driver is pulled low and Soft−Skip mode is activated. If this
pin is open (>3 V) for more than 130 ms, then the controller is placed in a fault mode.
This pin senses the primary current for PWM regulation. The maximum primary current
is limited to 1.0 V / R
CS
where R
CS
is the current sense resistor. Additionally, a ramp
resistor R
ramp
between the current sense node and this pin sets the compensation ramp
for improved stability.
−
The NCP1271’s powerful output is capable of driving the gates of large Qg MOSFETs.
This is the positive supply of the device. The operating range is between 10 V (min) and
20 V (max) with a UVLO start threshold 12.6 V (typ).
This pin provides (1) Lossless startup sequence (2) Double hiccup fault mode (3)
Memory for latch−off shutdown and (4) Device protection if V
CC
is shorted to GND.
3
CS
Current Sense
4
5
6
8
Gnd
Drv
V
CC
HV
IC Ground
Driver Output
Supply Voltage
High Voltage
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NCP1271
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values, T
J
=
−40°C
to +125°C, V
CC
= 14 V,
Characteristic
OSCILLATOR
Oscillation Frequency (65 kHz Version, T
J
= 25_C)
Oscillation Frequency (65 kHz Version, T
J
=
−40
to + 85_C)
Oscillation Frequency (65 kHz Version, T
J
=
−40
to + 125_C)
Oscillation Frequency (100 kHz Version, T
J
= 25_C)
Oscillation Frequency (100 kHz Version, T
J
=
−40
to +85_C)
Oscillation Frequency (100 kHz Version, T
J
=
−40
to +125_C)
Oscillator Modulation Swing, in Percentage of f
osc
Oscillator Modulation Swing Period
Maximum Duty Cycle (V
CS
= 0 V, V
FB
= 2.0 V)
GATE DRIVE
Gate Drive Resistance
Output High (V
CC
= 14 V, Drv = 300
W
to Gnd)
Output Low (V
CC
= 14 V, Drv = 1.0 V)
Rise Time from 10% to 90% (Drv = 1.0 nF to Gnd)
Fall Time from 90% to 10% (Drv = 1.0 nF to Gnd)
CURRENT SENSE
Maximum Current Threshold
Soft−Start Duration
Soft−Skip Duration
Leading Edge Blanking Duration
Propagation Delay (Drv =1.0 nF to Gnd)
Ramp Current Source Peak
Ramp Current Source Valley
SKIP
Default Standby Skip Threshold (Pin 1 = Open)
Skip Current (Pin 1 = 0 V, T
J
= 25_C)
Skip Level Reset (Note 5)
Transient Load Detection Level to Disable Soft−Skip Mode
EXTERNAL LATCH
Latch Protection Threshold
Latch Threshold Margin (V
latch−m
= V
CC(off)
−
V
latch
)
Noise Filtering Duration
Propagation Delay (Drv = 1.0 nF to Gnd)
SHORT−CIRCUIT FAULT PROTECTION
Time for Validating Short−Circuit Fault Condition
5. Please refer to Figure 39 for detailed description.
6. Guaranteed by design.
2
t
protect
−
130
−
ms
1
1
1
1
V
latch
V
latch−m
−
T
latch
7.1
0.6
−
−
8.0
1.2
13
100
8.7
−
−
−
V
V
ms
ns
2
1
1
2
V
skip
I
skip
V
skip−reset
V
TLD
−
26
5.0
2.6
1.2
43
5.7
2.85
−
56
6.5
3.15
V
mA
V
V
3
−
−
3
−
3
3
I
Limit
t
SS
t
SK
t
LEB
−
I
ramp(H)
I
ramp(L)
0.95
−
−
100
−
−
−
1.0
4.0
300
180
50
100
0
1.05
−
−
330
150
−
−
V
ms
ms
ns
ns
mA
mA
5
R
OH
R
OL
5
5
t
r
t
f
6.0
2.0
−
−
11
6.0
30
20
20
12
−
−
W
5
f
osc
61.75
58
55
95
89
85
−
−
75
65
65
65
100
100
100
"7.5
6.0
80
68.25
69
69
105
107
107
−
−
85
kHz
Pin
Symbol
Min
Typ
Max
Unit
HV = open, skip = open, FB = 2 V, CS = Ground, DRV = 1 nF, unless otherwise noted.)
5
5
5
−
−
D
max
%
ms
%
ns
ns
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