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M48T128Y-70PM1

Description
Real Time Clock 1M (128Kx8) 70ns
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size310KB,23 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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M48T128Y-70PM1 Overview

Real Time Clock 1M (128Kx8) 70ns

M48T128Y-70PM1 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeDIP
package instruction0.600 INCH, PLASTIC, MODULE, DIP-32
Contacts32
Reach Compliance Codeunknown
ECCN codeEAR99
Is SamacsysN
maximum clock frequency0.032 MHz
External data bus width8
Information access methodsPARALLEL, DIRECT ADDRESS
interrupt capabilityN
JESD-30 codeR-PDIP-P32
JESD-609 codee3
length42.8 mm
Humidity sensitivity level1
Number of terminals32
Number of timers
On-chip data RAM width8
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP32,.8
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
RAM (number of words)128000
Maximum seat height9.52 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationDUAL
shortest timeSECONDS
Maximum time at peak reflow temperatureNOT SPECIFIED
VolatileNO
width15.24 mm
uPs/uCs/peripheral integrated circuit typeTIMER, REAL TIME CLOCK
Base Number Matches1
M48T128Y
5.0 V, 1 Mbit (128 Kb x 8) TIMEKEEPER
®
SRAM
Not recommended for new design
Features
Integrated, ultra low power SRAM, real-time
clock, power-fail control circuit, battery, and
crystal
BCD coded year, month, day, date, hours,
minutes, and seconds
Automatic power-fail chip deselect and WRITE
protection
WRITE protect voltage
V
CC
= 4.5 to 5.5 V; 4.1 V
V
PFD
4.5 V
(V
PFD
= power-fail deselect voltage)
Conventional SRAM operation; unlimited
WRITE cycles
Software-controlled clock calibration for high
accuracy applications
32
10 years of data retention and clock operation
in the absence of power
Self-contained battery and crystal in the DIP
package
Pin and function compatible with JEDEC
standard 128 K x 8 SRAMs
RoHS compliant
– Lead-free second level interconnect
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September 2011
Doc ID 5746 Rev 7
1/23
www.st.com
1
This is information on a product still in production but not recommended for new designs.
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