HCF4029B
PRESETTABLE UP/DOWN COUNTER
BINARY OR BCD DECADE
s
s
s
s
s
s
s
s
s
s
MEDIUM SPEED OPERATION : 8MHz (Typ.)
at C
L
= 50pF and V
DD
- V
SS
= 10V
MULTI-PACKAGE PARALLEL CLOCKING
FOR SYNCHRONOUS HIGH SPEED
OUTPUT RESPONSE OR RIPPLE
CLOCKING FOR SLOW CLOCK INPUT RISE
AND FALL TIMES
"PRESET ENABLE" AND INDIVIDUAL "JAM"
INPUTS PROVIDED
BINARY OR DECADE UP/DOWN
COUNTING
BCD OUTPUTS IN DECADE MODE
QUIESCENT CURRENT SPECIF. UP TO 20V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DIP
SOP
ORDER CODES
PACKAGE
DIP
SOP
TUBE
HCF4029BEY
HCF4029BM1
T&R
HCF4029M013TR
DESCRIPTION
HCF4029B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4029B consists of a four stage binary or
BCD-decade up/down counter with provisions for
look ahead carry in both counting modes. The
PIN CONNECTION
inputs consist of a single CLOCK, CARRY IN
(CLOCK ENABLE), BINARY/DECADE, UP/
DOWN, PRESET ENABLE, and four individual
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT
signal are provided as outputs. A high PRESET
ENABLE signal allows information on the JAM
INPUTS to preset the counter to any state
asynchronously with the clock. A low on each JAM
line, when the PRESET-ENABLE signal is high,
resets the counter to its zero count. The counter
advances one count at the positive transition of
the clock when the CARRY-IN and PRESET
ENABLE signals are low. Advancement is
inhibited when the CARRY-IN or PRESET
ENABLE signals are high. The CARRY-OUT
September 2002
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HCF4029B
signal is normally high and the counter reaches its
maximum count in the UP mode or the minimum
count in the DOWN mode provided the CARRY-IN
signal is low. The CARRY-IN signal in the low
state can thus be considered a CLOCK ENABLE.
The CARRY-IN terminal must be connected to
V
SS
when not in use. Binary counting is
accomplished when the BINARY/DECODE input
is high; the counter counts in the decade mode
when the BINARY/DECADE input is low. The
counter counts Up when to UP/DOWN INPUT is
high, and Down when the UP/DOWN INPUT is
low. Multiple packages can be connected in either
a parallel clocking or a ripple clocking
arrangement.
Parallel
clocking
provides
synchronous control and, hence, a faster
response from all counting outputs. Ripple
clocking allows for longer clock input rise and fall
times.
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
15
5
SYMBOL
NAME AND FUNCTION
Clock Input
Carry In Input
Binary / Decade Select
Up/Down Select
Preset Enable Input
Jam Input Signals
Q Outputs
Carry Out Outputs
Negative Supply Voltage
Positive Supply Voltage
CLOCK
CARRY IN
BINARY/
9
DECADE
10
UP/DOWN
PRESET
1
ENABLE
4, 12, 13, 3 JAM1 to JAM4
6, 11, 14, 2
Q1 to Q4
7
CARRY OUT
V
SS
8
16
V
DD
FUNCTIONAL DIAGRAM
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