GAL16V8D-15LJN datasheet, PDF - EEWORLD Datasheet

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GAL16V8D-15LJN: DescriptionSPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V Low Power 15ns; CategoryProgrammable logic devices Programmable logic; File Size724KB，26 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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GAL16V8D-15LJN Overview

SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V Low Power 15ns

GAL16V8D-15LJN Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	QLCC
package instruction	QCCJ, LDCC20,.4SQ
Contacts	20
Reach Compliance Code	unknown
ECCN code	EAR99
Architecture	PAL-TYPE
maximum clock frequency	45.5 MHz
JESD-30 code	S-PQCC-J20
JESD-609 code	e3
length	8.9662 mm
Humidity sensitivity level	1
Dedicated input times	8
Number of I/O lines	8
Number of entries	18
Output times	8
Number of product terms	64
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC20,.4SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	250
power supply	5 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	8.9662 mm

GAL16V8D-15LJN Related Products

	GAL16V8D-15LJN	GAL16V8D-5LJ	GAL16V8D-25LJN	GAL16V8D-25QPN	GAL16V8D-25QJN	GAL16V8D-10LJN	GAL16V8D-25QPI	GAL16V8D-10LPN	GAL16V8D-15QJN
Description	SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V Low Power 15ns	SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V Low Power 5ns	SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V Low Power 25ns	SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V 1/4 Power 25ns	SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V 1/4 Power 25ns	SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V Low Power 10ns	SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V 1/4 Power 25ns	SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V Low Power 10ns	SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V 1/4 Power 15ns
Is it lead-free?	Lead free	Contains lead	Lead free	Lead free	Lead free	Lead free	Contains lead	Lead free	Lead free
Is it Rohs certified?	conform to	incompatible	conform to	conform to	conform to	conform to	incompatible	conform to	conform to
Maker	Lattice	Lattice	Lattice	Lattice	Lattice	Lattice	Lattice	Lattice	Lattice
Parts packaging code	QLCC	QLCC	QLCC	DIP	QLCC	QLCC	DIP	DIP	QLCC
package instruction	QCCJ, LDCC20,.4SQ	PLASTIC, LCC-20	LEAD FREE, PLASTIC, LCC-20	LEAD FREE, PLASTIC, DIP-20	LEAD FREE, PLASTIC, LCC-20	QCCJ, LDCC20,.4SQ	PLASTIC, DIP-20	LEAD FREE, PLASTIC, DIP-20	LEAD FREE, PLASTIC, LCC-20
Contacts	20	20	20	20	20	20	20	20	20
Reach Compliance Code	unknown	not_compliant	unknown	unknown	unknown	unknown	not_compliant	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Architecture	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE
maximum clock frequency	45.5 MHz	142.8 MHz	37 MHz	37 MHz	37 MHz	66.7 MHz	37 MHz	66.7 MHz	45.5 MHz
JESD-30 code	S-PQCC-J20	S-PQCC-J20	S-PQCC-J20	R-PDIP-T20	S-PQCC-J20	S-PQCC-J20	R-PDIP-T20	R-PDIP-T20	S-PQCC-J20
JESD-609 code	e3	e0	e3	e3	e3	e3	e0	e3	e3
length	8.9662 mm	8.9662 mm	8.9662 mm	26.162 mm	8.9662 mm	8.9662 mm	26.162 mm	26.162 mm	8.9662 mm
Dedicated input times	8	8	8	8	8	8	8	8	8
Number of I/O lines	8	8	8	8	8	8	8	8	8
Number of entries	18	18	18	18	18	18	18	18	18
Output times	8	8	8	8	8	8	8	8	8
Number of product terms	64	64	64	64	64	64	64	64	64
Number of terminals	20	20	20	20	20	20	20	20	20
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	85 °C	70 °C	70 °C
organize	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ	QCCJ	DIP	QCCJ	QCCJ	DIP	DIP	QCCJ
Encapsulate equivalent code	LDCC20,.4SQ	LDCC20,.4SQ	LDCC20,.4SQ	DIP20,.3	LDCC20,.4SQ	LDCC20,.4SQ	DIP20,.3	DIP20,.3	LDCC20,.4SQ
Package shape	SQUARE	SQUARE	SQUARE	RECTANGULAR	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	IN-LINE	CHIP CARRIER	CHIP CARRIER	IN-LINE	IN-LINE	CHIP CARRIER
Peak Reflow Temperature (Celsius)	250	225	250	NOT SPECIFIED	250	250	225	NOT SPECIFIED	250
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	15 ns	5 ns	25 ns	25 ns	25 ns	10 ns	25 ns	10 ns	15 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.572 mm	4.572 mm	4.572 mm	5.334 mm	4.572 mm	4.572 mm	5.334 mm	5.334 mm	4.572 mm
Maximum supply voltage	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.5 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.5 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	NO	YES	YES	NO	NO	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Tin/Lead (Sn85Pb15)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	J BEND	J BEND	J BEND	THROUGH-HOLE	J BEND	J BEND	THROUGH-HOLE	THROUGH-HOLE	J BEND
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	2.54 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm
Terminal location	QUAD	QUAD	QUAD	DUAL	QUAD	QUAD	DUAL	DUAL	QUAD
Maximum time at peak reflow temperature	40	30	40	NOT SPECIFIED	40	40	30	NOT SPECIFIED	40
width	8.9662 mm	8.9662 mm	8.9662 mm	7.62 mm	8.9662 mm	8.9662 mm	7.62 mm	7.62 mm	8.9662 mm
Humidity sensitivity level	1	1	1	-	1	1	-	-	1

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