GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
119, 165, & 209 BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165-, or 209-Bump BGA package
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–133 MHz 2.5
V or 3.3 V V
DD
2.5 V or 3.3 V I/O
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if
is
ica
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The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit
Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT,
NtRAM, NoBL or other pipelined read/double late write or
flow through read/single late write SRAMs, allow utilization
of all available bus bandwidth by eliminating the need to insert
deselect cycles when the device is switched from read to write
cycles.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
2.5
4.0
280
330
n/a
275
320
n/a
5.5
5.5
175
200
n/a
175
200
n/a
2.7
4.4
255
300
n/a
250
295
n/a
6.0
6.0
165
190
n/a
165
190
n/a
3.0
5.0
230
270
350
230
265
335
6.5
6.5
160
180
225
160
180
225
3.4
6.0
200
230
300
195
225
290
7.0
7.0
150
170
115
150
170
115
3.8
6.7
185
215
270
180
210
260
7.5
7.5
145
165
210
145
165
210
4.0
7.5
165
190
245
165
185
235
8.5
8.5
135
150
185
135
150
185
ns
ns
mA
mA
mA
mA
mA
mA
ns
ns
mA
mA
mA
mA
mA
mA
Pipeline
3-1-1-1
t
KQ
tCycle
in
th
rt
s
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
Curr (x18)
Curr (x36)
Curr (x72)
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
Curr (x18)
Curr (x36)
Curr (x72)
pa
2.5 V
Flow
Through
2-1-1-1
3.3 V
Th
e
x1
8a
nd
x3
6
2.5 V
Rev: 2.21 11/2004
1/38
n
ar
eN
ot
Functional Description
The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by
the user to operate in Pipeline or Flow Through mode.
Operating as a pipelined synchronous device, in addition to the
rising-edge-triggered registers that capture input signals, the
device incorporates a rising edge triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge-triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with
GSI's high performance CMOS technology and is available in
a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 &
x36), or 209-bump (x72) BGA package.
Re
co
m
m
en
d
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
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ew
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
De
sig
n
© 1999, GSI Technology
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z72 BGA Pin Description
Symbol
A
0
, A
1
An
DQ
A
DQ
B
DQ
C
DQ
D
DQ
E
DQ
F
DQ
G
DQ
H
B
A
, B
B
, B
C
,B
D,
B
E
, B
F
,
B
G
,B
H
NC
CK
W
E
1,
E
3
E
2
G
ZZ
FT
LBO
MCH
MCL
PE
ADV
ZQ
TMS
TDI
TDO
TCK
V
DD
V
SS
I
I
I
Type
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I
I
I
I
I
I
I
I
Write Enable. Writes all enabled bytes; active low
Chip Enable; active low
Chip Enable; active high
ica
ti o
n
sp
ec
if
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
Burst Address Counter Advance Enable; active high
is
pa
I
rt
s
I
O
I
I
I
I
in
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
V
DDQ
Rev: 2.21 11/2004
Th
e
x1
8a
nd
x3
6
th
3/38
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ot
Output Enable; active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
Must Connect Low
Re
co
m
I
Clock Input Signal; active high
m
—
No Connect
en
d
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D,
DQ
E
,
DQ
F
, DQ
G
, DQ
H
I/Os; active low
ed
fo
rN
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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I/O
Data Input and Output pins
De
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