Freescale Semiconductor
MPC5634M
Rev. 9.2, 01/2015
MPC5634M Microcontroller
Datasheet
This is the MPC5634M Datasheet set consisting of the following files:
• MPC5634M Datasheet
Addendum (MPC5634M_AD),
Rev. 1
• MPC5634M Datasheet
(MPC5634M),
Rev. 9
© Freescale Semiconductor, Inc., 2015. All rights reserved.
Freescale Semiconductor
Datasheet Addendum
MPC5634M_AD
Rev. 1.0, 01/2015
MPC5634M Microcontroller
Datasheet Addendum
This addendum describes corrections to the
MPC5634M
Microcontroller Datasheet,
order number MPC5634M.
For convenience, the addenda items are grouped by
revision. Please check our website at
http://www.freescale.com/powerarchitecture for the
latest updates.
The current version available of the
MPC5634M
Microcontroller Datasheet
is Revision 9.
Table of Contents
1
2
Addendum List for Revision 9 . . . . . . . . . . . . . . . . 2
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2
© Freescale Semiconductor, Inc., 2015. All rights reserved.
1
4
Addendum List for Revision 9
Table 1. MPC5634M Rev 9 Addendum
Location
Description
In “Temperature Sensor Electrical Characteristics” table, update the Min and Max value of
“Accuracy” parameter to -20
o
C and +20
o
C, respectively.
Section 4.11, “Temperature
Sensor Electrical
Characteristics”,
Page 81
2
Revision History
Table 2. Revision History Table
Rev. Number
1.0
Initial release.
Substantive Changes
Date of Release
12/2014
Table 2
provides a revision history for this datasheet addendum document.
MPC5634M_AD, Rev. 1.0
2
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Document Number: MPC5634M_AD
Rev. 1.0
01/2015
Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5634M
Rev. 9, 05/2012
MPC5634M
144 LQFP
20 mm x 20 mm
208 MAPBGA
17 mm x 17 mm
MPC5634M Microcontroller
Data Sheet
•
Operating Parameters
— Fully static operation, 0 MHz – 80 MHz (plus
2% frequency modulation - 82 MHz)
— –40
C
to 150
C
junction temperature
operating range
— Low power design
– Less than 400 mW power dissipation
(nominal)
– Designed for dynamic power management
of core and peripherals
– Software controlled clock gating of
peripherals
– Low power stop mode, with all clocks
stopped
— Fabricated in 90 nm process
— 1.2 V internal logic
— Single power supply with
5.0 V
5%
(4.5 V to 5.25 V) with
internal regulator to provide 3.3 V and 1.2 V for
the core
— Input and output pins with
5.0 V
5%
(4.5 V to 5.25 V) range
– 35%/65% V
DDE
CMOS switch levels (with
hysteresis)
– Selectable hysteresis
– Selectable slew rate control
— Nexus pins powered by 3.3 V supply
— Designed with EMI reduction techniques
– Phase-locked loop
– Frequency modulation of system clock
frequency
– On-chip bypass capacitance
– Selectable slew rate and drive strength
•
176 LQFP
24 mm x 24 mm
High performance e200z335 core processor
— 32-bit
Power Architecture Book E
programmer’s model
— Variable Length Encoding Enhancements
– Allows Power Architecture instruction set to
be optionally encoded in a mixed 16 and
32-bit instructions
– Results in smaller code size
— Single issue, 32-bit
Power Architecture
technology
compliant CPU
— In-order execution and retirement
— Precise exception handling
— Branch processing unit
– Dedicated branch address calculation adder
– Branch acceleration using Branch
Lookahead Instruction Buffer
— Load/store unit
– One-cycle load latency
– Fully pipelined
– Big and Little Endian support
– Misaligned access support
– Zero load-to-use pipeline bubbles
— Thirty-two 64-bit general purpose registers
(GPRs)
— Memory management unit (MMU) with
16-entry fully-associative translation look-aside
buffer (TLB)
— Separate instruction bus and load/store bus
— Vectored interrupt support
— Interrupt latency < 120 ns @ 80 MHz
(measured from interrupt request to execution of
first instruction of interrupt exception handler)
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2012. All rights reserved.
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