FS7140, FS7145
Programmable Phase-
Locked Loop Clock
Generator
Description
The FS7140 or FS7145 is a monolithic CMOS clock generator/
regenerator IC designed to minimize cost and component count in a
variety of electronic systems. Via the I
2
C−bus interface, the
FS7140/45 can be adapted to many clock generation requirements.
The length of the reference and feedback dividers, their fine
granularity and the flexibility of the post divider make the FS7140/45
the most flexible stand−alone PLL clock generator available.
Features
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SOIC−16
01 SUFFIX
CASE 751BA
SSOP−16
02 SUFFIX
CASE 565AE
•
Extremely Flexible and Low−jitter Phase Locked Loop (PLL)
•
•
•
•
•
•
•
•
•
•
•
•
Frequency Synthesis
No External Loop Filter Components Needed
150 MHz CMOS or 340 MHz PECL Outputs
Completely Configurable via I
2
C−bus
Up to Four FS714x can be Used on a Single I
2
C−bus
3.3 V Operation
Independent On−chip Crystal Oscillator and External Reference
Input
Very Low “Cumulative” Jitter
Pb−Free Packages are Available
PIN CONNECTIONS
SCL
SDA
ADDR0
VSS
XIN
XOUT
ADDR1
VDD
1
CLKN
CLKP
VDD
*
REF
VSS
N/C
IPRG
(Top View)
* FS7140 pin 13 = N/C
*
FS7145 pin 13 = SYNC
Applications
Precision Frequency Synthesis
Low−frequency Clock Multiplication
Video Line−locked Clock Generation
Laser Beam Printers (FS7145)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
October, 2011
−
Rev. 7
1
Publication Order Number:
FS7140/D
FS7140, FS7145
Figure 1. Device Block Diagram
Table 1. PIN DESCRIPTIONS*
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
DI
DIO
DI
D
P
AI
AO
DI
D
P
AI
−
P
DI
U
−
DI
U
P
DO
DO
Name
SCL
SDA
ADDR0
VSS
XIN
XOUT
ADDR1
VDD
IPRG
n/c
VSS
REF
n/c
SYNC
VDD
CLKP
CLKN
Description
Serial interface clock (requires an external pull−up)
Serial interface data input/output (requires an external pull−up)
Address select bit “0”
Ground
Crystal oscillator feedback
Crystal oscillator drive
Address select bit “1”
Power supply (+3.3 V nominal)
PECL current drive programming
No connection
Ground
Reference frequency input
FS7140 = No connection
FS7145 = Synchronization input
Power supply (+3.3 V nominal)
Clock output
Inverted clock output
*Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull−up; DI
D
= Input with Internal Pull−down; DIO = Digital
Input/Output; DI−3 = Three−Level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin
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FS7140, FS7145
ELECTRICAL SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
1
V
O
I
IK
I
OK
T
S
T
A
T
J
Parameter
Supply voltage, dc (V
SS
= ground)
Input voltage, dc
Output voltage, dc
Input clamp current, dc (V
I
< 0 or V
I
> V
DD
)
Output clamp current, dc (V
I
< 0 or V
I
> V
DD
)
Storage temperature range (non−condensing)
Ambient temperature range, under bias
Junction temperature
Re−flow solder profile
Input static discharge voltage protection
(MIL−STD 883E, Method 3015.7)
Per IPC/JEDEC J−STD−020B
2
kV
Min
V
SS
−
0.5
V
SS
−
0.5
V
SS
−
0.5
−50
−50
−65
−55
Typ
Max
4.5
V
DD
+ 0.5
V
DD
+ 0.5
50
50
150
125
150
Units
V
V
V
mA
mA
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
WARNING:
ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to
a high-energy electrostatic discharge.
Table 3. OPERATING CONDITIONS
Symbol
V
DD
T
A
Supply voltage
Ambient operating temperature range
Parameter
Min
3.0
0
Typ
3.3
Max
3.6
70
Units
V
°C
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FS7140, FS7145
Table 4. DC ELECTRICAL SPECIFICATIONS
(Note 1)
Parameter
OVERALL
Supply current, dynamic
I
DD
CMOS mode; F
XTAL
= 15 MHz; F
VCO
= 400 MHz; F
CLK
= 200 MHz; does
not include load current
SHUT1, SHUT2 bit both “1”
35
mA
Symbol
Conditions/Description
Min
Typ
Max
Units
Supply current, static
I
DDL
V
IH
V
IL
V
hys
I
I
I
OL
400
700
mA
SERIAL COMMUNICATION I/O (SDA, SCL)
High−level input voltage
Low−level input voltage
Hysteresis voltage
Input leakage current
Low−level output sink current (SDA)
0.8*V
DD
0.2*V
DD
0.33*V
DD
SDA, SCL in read condition
SDA in acknowledge condition;
V
SDA
= 0.4 V
−10
5
14
+10
V
V
V
mA
mA
ADDRESS SELECT INPUT (ADDR0, ADDR1)
High−level input voltage
Low−level input voltage
High−level input current (pull−down)
Low−level input current
REFERENCE FREQUENCY INPUT (REF)
High−level input voltage
Low−level input voltage
High−level input current
Low−level input current (pull−down)
SYNC CONTROL INPUT (SYNC)
High−level input voltage
Low−level input voltage
High−level input current
Low−level input current (pull−down)
CRYSTAL OSCILLATOR INPUT (XIN)
Threshold bias voltage
High−level input current
Low−level input current
Crystal frequency
Recommended crystal load
capacitance*
V
TH
I
IH
I
IL
F
X
C
L(XTAL)
V
XIN
= V
DD
V
XIN
= GND
Fundamental mode
For best matching with internal crystal
oscillator load
16−18
V
DD
/2
40
−40
35
V
mA
mA
MHz
pF
V
IH
V
IL
I
IH
I
IL
V
REF
= V
DD
V
REF
= 0 V
−1
−30
V
DD
−1.0
0.8
1
V
V
mA
mA
V
IH
V
IL
I
IH
I
IL
V
REF
= V
DD
V
REF
= 0 V
−1
−30
V
DD
−1.0
0.8
1
V
V
mA
mA
V
IH
V
IL
I
IH
I
IL
V
ADDRx
= V
DD
V
ADDRx
= 0 V
−1
30
1
V
DD
−1.0
0.8
V
V
mA
mA
CRYSTAL OSCILLATOR OUTPUT (XOUT)
High−level output source current
Low−level output sink current
PECL CURRENT PROGRAM I/O (IPRG)
Low−level input current
I
IL
I
OH
V
IPRG
= 0 V; PECL mode
V
O
= 2.0 V
−10
10
mA
I
OH
I
OL
V
XOUT
= 0
V
XOUT
= V
DD
−8.5
11
mA
mA
CLOCK OUTPUTS, CMOS MODE (CLKN, CLKP)
High−level output source current
19
mA
1. Unless otherwise stated, V
DD
= 3.3 V
±
10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characteriza-
tion data are
±
3s from typical. Negative currents indicate flows out of the device.
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FS7140, FS7145
Table 4. DC ELECTRICAL SPECIFICATIONS
(Note 1)
Parameter
Symbol
Conditions/Description
Min
Typ
Max
Units
CLOCK OUTPUTS, CMOS MODE (CLKN, CLKP)
Low−level output sink current
I
OL
V
IPRG
V
O
= 0.4 V
V
IPRG
will be clamped to this level
when a resistor is connected from
VDD to IPRG
I
IPRG
−
(V
VDD
−
V
IPRG
) / R
SET
13
I
Z
−10
10
mA
−35
mA
CLOCK OUTPUTS, PECL MODE (CLKN, CLKP)
IPRG bias voltage
V
DD
/3
V
IPRG bias current
Sink current to IPRG current ratio
Tristate output current
I
IPRG
3.5
mA
1. Unless otherwise stated, V
DD
= 3.3 V
±
10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characteriza-
tion data are
±
3s from typical. Negative currents indicate flows out of the device.
Table 5. AC TIMING SPECIFICATIONS
(Note 2)
Parameter
OVERALL
Output frequency*
VCO frequency*
CMOS mode rise time*
CMOS mode fall time*
PECL mode rise time*
PECL mode fall time*
Input frequency
Reference high time
Reference low time
SYNC CONTROL INPUT (SYNC)
Sync high time
Sync low time
CLOCK OUTPUT (CLKN, CLKP)
Duty cycle (CMOS mode)*
Duty cycle (PECL mode)*
Jitter, long term (s
y
(t))*
t
j(LT)
Measured at 1.4 V
Measured at zero crossings of
(V
CLKP
−
V
CLKN
)
50
50
%
%
ps
t
SYNCH
t
SYNCL
For orderly CLK stop/start
For orderly CLK stop/start
3
3
T
CLK
f
o(max)
f
VCO
t
r
t
f
t
r
t
f
F
REF
t
REHF
t
REFL
3
3
C
L
= 7 pF
C
L
= 7 pF
C
L
= 7 pF; R
L
= 65 ohm
C
L
= 7 pF; R
L
= 65 ohm
CMOS outputs
PECL outputs
0
0
40
1
1
1
1
80
150
300
400
MHz
ns
ns
ns
ns
MHz
ns
ns
MHz
Symbol
Conditions/Description
Min
Typ
Max
Units
REFERENCE FREQUENCY INPUT (REF)
For valid programming solutions. Long-term (or cumulative) jitter specified is
RMS position error of any edge compared with an ideal clock generated from
the same reference frequency. It is measured with a time interval analyzer us-
ing a 500 microsecond window, using statistics gathered over 1000 samples.
FREF/NREF > 1000 kHz
FREF/NREF
^
500 kHz
FREF/NREF
^
250 kHz
FREF/NREF
^
125 kHz
FREF/NREF
^
62.5 kHz
FREF/NREF
^
31.5 kHz
25
50
100
190
240
300
75
50
ps
ps
ps
ps
ps
ps
ps
ps
Jitter, period (peak−peak)*
t
j(DP)
40 MHz < VCO frequency < 100 MHz
VCO frequency > 100 MHz
2. Unless otherwise stated, V
DD
= 3.3 V
±
10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization
data are
±
3s from typical.
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