GS882Z18BGB-150V datasheet, PDF

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GS882Z18BGB-150V: Description256K X 36 ZBT SRAM, 6.5 ns, PBGA119; Categorystorage storage; File Size787KB，33 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS882Z18BGB-150V Overview

256K X 36 ZBT SRAM, 6.5 ns, PBGA119

GS882Z18BGB-150V Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	compli
ECCN code	3A991.B.2.B
Maximum access time	7.5 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY
JESD-30 code	R-PBGA-B119
JESD-609 code	e1
length	22 mm
memory density	9437184 bi
Memory IC Type	ZBT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.99 mm
Maximum supply voltage (Vsup)	2 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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GS882Z18/36B(B/D)-xxxV

119-bump and 165-bump BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip parity encoding and error detection

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-bump BGA and 165-bump FPBGA

packages

• RoHS-compliant 119-bump and 165-bump BGA packages

available

9Mb Pipelined and Flow Through

Synchronous NBT SRAM

250 MHz–150 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GGS882Z18/36B(B/D)-xxxV may be configured by the

user to operate in Pipeline or Flow Through mode. Operating

as a pipelined synchronous device, in addition to the rising-

edge-triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS882Z18/36B(B/D)-xxxV is implemented with GSI's

high performance CMOS technology and is available in

JEDEC-standard 119-bump BGA and 165-bump FPBGA

packages.

Functional Description

The GS882Z18/36B(B/D)-xxxV is a 9Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Paramter Synopsis

-250

-200

3.0

5.0

165

185

6.5

140

155

-150

3.8

6.7

140

160

7.5

128

145

Unit

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

tCycle

Curr (x18)

Curr (x32/x36)

3.0

4.0

195

220

5.5

155

175

Flow Through

2-1-1-1

Rev: 1.04 6/2006

1/33

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

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