INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4094B
MSI
8-stage shift-and-store bus register
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
DESCRIPTION
The HEF4094B is an 8-stage serial shift register having a
storage latch associated with each stage for strobing data
from the serial input to parallel buffered 3-state outputs
O
0
to O
7
. The parallel outputs may be connected directly
to common bus lines. Data is shifted on positive-going
clock transitions. The data in each shift register stage is
transferred to the storage register when the strobe (STR)
input is HIGH. Data in the storage register appears at the
outputs whenever the output enable (EO) signal is HIGH.
HEF4094B
MSI
Two serial outputs (O
s
and O’
s
) are available for cascading
a number of HEF4094B devices. Data is available at O
s
on
positive-going clock edges to allow high-speed operation
in cascaded systems in which the clock rise time is fast.
The same serial information is available at O’
s
on the next
negative-going clock edge and provides cascading
HEF4094B devices when the clock rise time is slow.
Fig.2 Pinning diagram.
HEF4094BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4094BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4094BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
D
CP
Fig.1 Functional diagram.
STR
data input
clock input
strobe input
EO
O
s
, O’
s
O
0
to O
7
output enable input
serial outputs
parallel outputs
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
January 1995
2
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Philips Semiconductors
January 1995
8-stage shift-and-store bus register
3
Product specification
Fig.3 Logic diagram.
HEF4094B
MSI
Fig.4 One D-latch.
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
FUNCTION TABLE
INPUTS
CP
EO
L
L
H
H
H
H
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4.
5.
= positive-going transition
= negative-going transition
STR
X
X
L
H
H
H
D
X
X
X
L
H
H
PARALLEL OUTPUTS
O
0
Z
Z
nc
L
H
nc
O
n
Z
Z
nc
O
n-1
O
n-1
nc
SERIAL OUTPUTS
O
s
O’
6
nc
O’
6
O’
6
O’
6
nc
O’
s
nc
O
7
nc
nc
nc
O
7
HEF4094B
MSI
6. Z = high impedance off state
7. nc = no change
8. O’
6
= the information in the seventh shift register stage
At the positive clock edge the information in the 7th register stage is transferred to the 8th register stage and the
O
s
output.
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
input transition times
≤
20 ns
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
2100 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
9700 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
26 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
CP
→
O
s
HIGH to LOW
5
10
15
5
LOW to HIGH
CP
→
O’
s
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
CP
→
O
n
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
STR
→
O
n
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
Output transition times
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
10
15
t
TLH
t
THL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
135
65
50
105
50
40
105
50
40
105
50
40
165
75
55
150
70
55
110
50
35
100
45
35
60
30
20
60
30
20
270
130
100
210
100
80
210
100
80
210
100
80
330
150
110
300
140
110
220
100
70
200
90
70
120
60
40
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
TYP.
MAX.
HEF4094B
MSI
TYPICAL EXTRAPOLATION
FORMULA
108 ns
+
(0,55 ns/pF) C
L
54 ns
+
(0,23 ns/pF) C
L
42 ns
+
(0,16 ns/pF) C
L
78 ns
+
(0,55 ns/pF) C
L
39 ns
+
(0,23 ns/pF) C
L
32 ns
+
(0,16 ns/pF) C
L
78 ns
+
(0,55 ns/pF) C
L
39 ns
+
(0,23 ns/pF) C
L
32 ns
+
(0,16 ns/pF) C
L
78 ns
+
(0,55 ns/pF) C
L
39 ns
+
(0,23 ns/pF) C
L
32 ns
+
(0,16 ns/pF) C
L
138 ns
+
(0,55 ns/pF) C
L
64 ns
+
(0,23 ns/pF) C
L
47 ns
+
(0,16 ns/pF) C
L
123 ns
+
(0,55 ns/pF) C
L
59 ns
+
(0,23 ns/pF) C
L
47 ns
+
(0,16 ns/pF) C
L
83 ns
+
(0,55 ns/pF) C
L
39 ns
+
(0,23 ns/pF) C
L
27 ns
+
(0,16 ns/pF) C
L
73 ns
+
(0,55 ns/pF) C
L
34 ns
+
(0,23 ns/pF) C
L
27 ns
+
(0,16 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
January 1995
5
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