HMU16, HMU17
TM
Data Sheet
November 1999
File Number
2803.4
16 x 16-Bit CMOS Parallel Multipliers
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The HMU16 and HMU17 are high speed, low power CMOS
16-bit x 16-bit multipliers ideal for fast, real time digital signal
processing applications.
The X and Y operands along with their mode controls (TCX
and TCY) have 17-bit input registers. The mode controls
independently specify the operands as either two’s
complement or unsigned magnitude format, thereby allowing
mixed mode multiplication operations.
Two 16-bit output registers are provided to hold the most and
least significant halves of the result (MSP and LSP). For
asynchronous output, these registers may be made
transparent through the use of the Feedthrough Control
(FT).
Additional inputs are provided for format adjustment and
rounding. The Format Adjust control (FA) allows the user to
select either a left shifted 31-bit product or a full 32-bit
product, whereas the round control (RND) provides the
capability of rounding the most significant portion of the
result.
The HMU16 has independent clocks (CLKX, CLKY, CLKL,
CLKM) associated with each of these registers to maximize
throughput and simplify bus interfacing. The HMU17 has
only a single clock input (CLK), but makes use of three
register enables (ENX, ENY and ENP). The ENX and ENY
inputs control the X and Y Input Registers, while ENP
controls both the MSP and LSP Output Registers. This
configuration facilitates the use of the HMU17 for
microprogrammed systems.
The two halves of the product may be routed to a single
16-bit three-state output port via a multiplexer, and in
addition, the LSP is connected to the Y-input port through a
separate three-state buffer.
Features
• 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product
• High-Speed (35ns) Clocked Multiply Time
• Low Power Operation
- I
CCSB
= 500µA Maximum
- I
CCOP
= 7.0mA Maximum at 1MHz
• Supports Two’s Complement, Unsigned Magnitude and
Mixed Mode Multiplication
• HMU16 is Compatible with the AM29516, LMU16,
IDT7216 and the CY7C516
• HMU17 is Compatible with the AM29517, LMU17,
IDT7217 and the CY7C517
• TTL Compatible Inputs/Outputs
• Three-State Outputs
Applications
• Fast Fourier Transform Analysis
• Digital Filtering
• Graphic Display Systems
• Image Processing
• Radar and Sonar
• Speech Synthesis and Recognition
Ordering Information
PART NUMBER
HMU16JC-35
HMU16JC-45
HMU16GC-35
HMU16GC-45
HMU17JC-35
HMU17JC-45
HMU17GC-35
HMU17GC-45
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
68 Ld PLCC
68 Ld PLCC
68 Ld CPGA
68 Ld CPGA
68 Ld PLCC
68 Ld PLCC
68 Ld CPGA
68 Ld CPGA
PKG.
NO.
N68.95
N68.95
G68.B
G68.B
N68.95
N68.95
G68.B
G68.B
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
HMU16, HMU17
Pinouts
68 LEAD PLCC
TOP VIEW
NC
CLKM (ENP)
OEP
FA
FT
MSPSEL
GND
GND
V
CC
V
CC
TCY
TCX
RND
CLKX (ENX)
X15
X14
X13
9 8 7 6 5 4 3 2 1 6867666564636261
P15, P31
P14, P30
P13, P29
P12, P28
P11, P27
P10, P26
P9, P25
P8, P24
P7, P23
P6, P22
P5, P21
P4, P20
P3, P19
P2, P18
P1, P17
P0, P16
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27282930313233 34 35 36 37 38 39 40 41 42 43
Y15, P15
Y14, P14
Y13, P13
Y12, P12
Y11, P11
Y10, P10
Y9, P9
Y8, P8
Y7, P7
Y6, P6
Y5, P5
Y4, P4
Y3, P3
Y2, P2
Y1, P1
Y0, P0
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
OEL
CLKL (CLK)
CLKY (ENY)
68 LEAD CPGA
TOP VIEW
11
N/C
X13
X15
CLKX
(ENX)
RND
TCY
V
CC
GND
MSP
SEL
FT
OEP
CLKM
(ENP)
P30/
P14
P28/
P12
P26/
P10
P24/
P8
P22/
P6
P20/
P4
P18/
P2
Y2/P2 Y4/P4
Y6/P6 Y8/P8
Y10/
P10
Y11/
P11
G
Y12/
P12
Y13/
P13
H
Y14/
P14
Y15/
P15
J
P16/
P0
N/C
K
L
10
X11
X12
X14
TCX
V
CC
GND
FA
N/C
P31/
P15
P29/
P13
P27/
P11
P25/
P9
P23/
P7
P21/
P5
P19/
P3
P17/
P1
9
X9
X10
8
X7
X8
7
X5
X6
6
X3
X4
5
X1
X2
4
OEL
CLKY
(ENY)
N/C
X0
CLKL
(CLK)
Y0/P0
3
2
1
A
Y1/P1
B
Y3/P3 Y5/P5
C
D
Y7/P7 Y9/P9
E
F
2
HMU16, HMU17
Functional Block Diagrams
HMU16
X0 - 15 TCX
RND
TCY
Y0 - 15/PO - 15
REGISTER
REGISTER
REGISTER
OEL
CLKX
CLKY
MULTIPLIER ARRAY
FA
FT
CLKM
CLKL
MSPSEL
OEP
FORMAT ADJUST
MSP
RESISTER
LSP
RESISTER
MULTIPLEXER
P16 - 31/PO - 15
HMU17
X0 - 15 TCX TCX
RND
TCY
Y0 - 15/PO - 15
REGISTER
REGISTER
REGISTER
CLK
ENX
ENY
MULTIPLIER ARRAY
OEL
FA
FT
FORMAT ADJUST
MSP
RESISTER
LSP
RESISTER
ENP
MSPSEL
MULTIPLEXER
OEP
P16 - 31/PO - 15
3
HMU16, HMU17
Pin Description
SYMBOL
V
CC
GND
X0-X15
Y0-Y15/
P0-P15
P16-P31/
P0-P15
TCY, TCX
FT
FA
PLCC PIN
NUMBER
1, 68
2, 3
47-59, 61-63
27-42
I
I/O
TYPE
DESCRIPTION
V
CC
. The +5V power supply pins. A 0.1µF capacitor between the V
CC
and GND pins is
recommended.
GND. The device ground.
X-Input Data. These 16 data inputs provide the multiplicand which may be in two's complement
or unsigned magnitude format.
Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which may be in two's
complement or unsigned magnitude format. It may also be used for output of the Least Significant
Product (LSP).
Output Data. This 16-bit port may provide either the MSP (P16-31) or the LSP (P0-15).
Two's Complement Control. Input data is interpreted as two's complement when this control is
HIGH. A LOW indicates the data is to be interpreted as unsigned magnitude format.
Feed through Control. When this control is HIGH, both the MSP and LSP Registers are
transparent. When LOW, the registers are latched by their associated clock signals.
Format Adjust Control. A full 32-bit product is selected when this control line is HIGH. A LOW on
this control line selects a left shifted 31-bit product with the sign bit replicated in the LSP. This
control is normally HIGH, except for certain two's complement integer and fractional
applications.
Round Control. When this control is HIGH, a one is added to the Most Significant Bit (MSB) of the
LSP. This position is dependent on the FA control; FA = HIGH indicates RND adds to the 2-15 bit
(P15), and FA = LOW indicates RND adds to the 2
-16
bit (P14).
Output Multiplexer Control. When this control is LOW, the MSP is available for output at the
dedicated output port, and the LSP is available at the Y-input/LSP output port. When MSPSEL is
HIGH, the LSP is available at both ports and the MSP is not available for output.
Y-In/P0-15 Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high
impedance state. This state is required for Ydata input. When OEL is LOW, the port is enabled for
LSP output.
P16-31/P0-15 Output Port Three-State Control. A LOW on this control line enables the output
port. When OEP is HIGH, the output drivers are in the high impedance state.
10-25
66, 67
5
6
O
I
I
I
RND
65
I
MSPSEL
4
I
OEL
46
I
OEP
7
I
THE FOLLOWING PIN DESCRIPTIONS APPLY TO THE HMU16 ONLY
CLKX
CLKY
CLKM
CLKL
64
44
8
45
I
I
I
I
X-Register Clock. The rising edge of this clock loads the X-data Input Register along with the TCX
and RND Registers.
Y-Register Clock. The rising edge of this clock loads the Y-data Input Register along with the TCY
and RND Registers.
MSP Register Clock. The rising edge of CLKM loads the Most Significant Product (MSP) Register.
LSP Register Clock. The rising edge of CLKL loads the Least Significant Product (LSP) Register.
THE FOLLOWING PIN DESCRIPTIONS APPLY TO THE HMU17 ONLY
CLK
ENX
ENY
ENP
45
64
44
8
I
I
I
I
Clock. The rising edge of this clock will load all enabled registers.
X-Register Enable. When ENX is LOW, the X-register is enabled; X-input data and TCX will be
latched at the rising edge of CLK. When ENX is high, the X-register is in a hold mode.
Y-Register Enable. ENY enables the Y-register. (See ENX).
Product Register Enable. ENP enables the Product Register. Both the MSP and LSP
Sections are enabled by ENP. (See ENX).
4
HMU16, HMU17
Functional Description
The HMU16/HMU17 are high speed 16 x 16-bit multipliers
designed to perform very fast multiplication of two 16-bit
binary numbers. The two 16-bit operands (X and Y) may be
independently specified as either two's complement or
unsigned magnitude format by the two's complement
controls (TCX and TCY). When either of these control lines
is LOW, the respective operand is treated as an unsigned
16-bit value; and when it is HIGH, the operand is treated as
a signed value represented in two's complement format. The
operands along with their respective controls are latched at
the rising edge of the associated clock signal. The HMU16
accomplishes this through the use of independent clock
inputs for each of the Input Registers (CLKX and CLKY),
while the HMU17 utilizes a single clock signal (CLK) along
with the X and Y register enable inputs (ENX and ENY).
Input controls are also provided for rounding and format
adjustment of the 32-bit product. The Round input (RND) is
provided to accommodate rounding of the most significant
portion of the product by adding one to the Most Significant
Bit (MSB) of the LSP Register. The position of the MSB is
dependent on the state of the Format Adjust Control (see Pin
Descriptions and Multiplier Input/Output Format Tables). The
Round input is latched into the RND Register whenever
either of the input registers is clocked. The Format Adjust
control (FA) allows the product output to be formatted. When
the FA control is HIGH, a full 32-bit product is output; and
when FA is LOW, a left-shifted 31-bit product is output with
the sign bit replicated in bit position 15 of the LSP. The FA
control must be HIGH for unsigned magnitude, and mixed
mode multiplication operations. It may be LOW for certain
two's complement integer and fractional operations only (see
Multiplier Input/ Output Formats Table).
The HMU16/HMU17 multipliers are equipped with two 16-bit
Output Registers (MSP and LSP) which are provided to hold
the most and least significant portions of the resultant
product respectively. The HMU16 uses independent clocks
(CLKM and CLKL) for latching the two output registers, while
the HMU17 uses a single clock input (CLK) along with the
Product Latch Enable (ENP). The MSP and LSP Registers
may also be made transparent for asynchronous output
through the use of the Feed through Control (FT). There are
two output configurations which may be selected when using
the HMU16/HMU17 multipliers. The first configuration allows
the simultaneous access of the most and least significant
halves of the product. When the MSPSEL input is LOW, the
Most Significant Product will be available at the dedicated
output port (P16-31/P0-15). The Least Significant Product is
simultaneously available at the bidirectional port shared with
the Y-inputs (Y0-15/P0-15) through the use of the LSP
output enable (OEL). The other output configuration involves
multiplexing the MSP and LSP Registers onto the dedicated
output port through the use of the MSPSEL control. When
the MSPSEL control is LOW, the Most Significant Product
will be available at the dedicated output port; and when
MSPSEL is HIGH, the Least Significant Product will be
available at this port. This configuration allows access of the
entire 32-bit product by a 16-bit wide system bus.
5
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