HMU16GC-45 datasheet, PDF - EEWORLD Datasheet

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HMU16GC-45: Description16-BIT, DSP-MULTIPLIER, CPGA68; Categorysemiconductor The embedded processor and controller; File Size214KB，13 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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HMU16GC-45 Overview

16-BIT, DSP-MULTIPLIER, CPGA68

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HMU16, HMU17

Data Sheet

November 1999

File Number

2803.4

16 x 16-Bit CMOS Parallel Multipliers

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The HMU16 and HMU17 are high speed, low power CMOS

16-bit x 16-bit multipliers ideal for fast, real time digital signal

processing applications.

The X and Y operands along with their mode controls (TCX

and TCY) have 17-bit input registers. The mode controls

independently specify the operands as either two’s

complement or unsigned magnitude format, thereby allowing

mixed mode multiplication operations.

Two 16-bit output registers are provided to hold the most and

least significant halves of the result (MSP and LSP). For

asynchronous output, these registers may be made

transparent through the use of the Feedthrough Control

(FT).

Additional inputs are provided for format adjustment and

rounding. The Format Adjust control (FA) allows the user to

select either a left shifted 31-bit product or a full 32-bit

product, whereas the round control (RND) provides the

capability of rounding the most significant portion of the

result.

The HMU16 has independent clocks (CLKX, CLKY, CLKL,

CLKM) associated with each of these registers to maximize

throughput and simplify bus interfacing. The HMU17 has

only a single clock input (CLK), but makes use of three

inputs control the X and Y Input Registers, while ENP

controls both the MSP and LSP Output Registers. This

configuration facilitates the use of the HMU17 for

microprogrammed systems.

The two halves of the product may be routed to a single

16-bit three-state output port via a multiplexer, and in

addition, the LSP is connected to the Y-input port through a

separate three-state buffer.

Features

• 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product

• High-Speed (35ns) Clocked Multiply Time

• Low Power Operation

- I

CCSB

= 500µA Maximum

- I

CCOP

= 7.0mA Maximum at 1MHz

• Supports Two’s Complement, Unsigned Magnitude and

Mixed Mode Multiplication

• HMU16 is Compatible with the AM29516, LMU16,

IDT7216 and the CY7C516

• HMU17 is Compatible with the AM29517, LMU17,

IDT7217 and the CY7C517

• TTL Compatible Inputs/Outputs

• Three-State Outputs

Applications

• Fast Fourier Transform Analysis

• Digital Filtering

• Graphic Display Systems

• Image Processing

• Radar and Sonar

• Speech Synthesis and Recognition

Ordering Information

PART NUMBER

HMU16JC-35

HMU16JC-45

HMU16GC-35

HMU16GC-45

HMU17JC-35

HMU17JC-45

HMU17GC-35

HMU17GC-45

TEMP.

RANGE (

0 to 70

PACKAGE

68 Ld PLCC

68 Ld CPGA

68 Ld PLCC

68 Ld CPGA

PKG.

NO.

N68.95

G68.B

N68.95

G68.B

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil and Design is a trademark of Intersil Americas Inc.

HMU16, HMU17

Pin Description

SYMBOL

GND

X0-X15

Y0-Y15/

P0-P15

P16-P31/

P0-P15

TCY, TCX

PLCC PIN

NUMBER

1, 68

2, 3

47-59, 61-63

27-42

I/O

TYPE

DESCRIPTION

. The +5V power supply pins. A 0.1µF capacitor between the V

and GND pins is

recommended.

GND. The device ground.

X-Input Data. These 16 data inputs provide the multiplicand which may be in two's complement

or unsigned magnitude format.

Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which may be in two's

complement or unsigned magnitude format. It may also be used for output of the Least Significant

Product (LSP).

Output Data. This 16-bit port may provide either the MSP (P16-31) or the LSP (P0-15).

Two's Complement Control. Input data is interpreted as two's complement when this control is

HIGH. A LOW indicates the data is to be interpreted as unsigned magnitude format.

Feed through Control. When this control is HIGH, both the MSP and LSP Registers are

transparent. When LOW, the registers are latched by their associated clock signals.

Format Adjust Control. A full 32-bit product is selected when this control line is HIGH. A LOW on

this control line selects a left shifted 31-bit product with the sign bit replicated in the LSP. This

control is normally HIGH, except for certain two's complement integer and fractional

applications.

Round Control. When this control is HIGH, a one is added to the Most Significant Bit (MSB) of the

LSP. This position is dependent on the FA control; FA = HIGH indicates RND adds to the 2-15 bit

(P15), and FA = LOW indicates RND adds to the 2

-16

bit (P14).

Output Multiplexer Control. When this control is LOW, the MSP is available for output at the

dedicated output port, and the LSP is available at the Y-input/LSP output port. When MSPSEL is

HIGH, the LSP is available at both ports and the MSP is not available for output.

Y-In/P0-15 Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high

impedance state. This state is required for Ydata input. When OEL is LOW, the port is enabled for

LSP output.

P16-31/P0-15 Output Port Three-State Control. A LOW on this control line enables the output

port. When OEP is HIGH, the output drivers are in the high impedance state.

10-25

66, 67

RND

MSPSEL

OEL

OEP

THE FOLLOWING PIN DESCRIPTIONS APPLY TO THE HMU16 ONLY

CLKX

CLKY

CLKM

CLKL

X-Register Clock. The rising edge of this clock loads the X-data Input Register along with the TCX

and RND Registers.

Y-Register Clock. The rising edge of this clock loads the Y-data Input Register along with the TCY

and RND Registers.

MSP Register Clock. The rising edge of CLKM loads the Most Significant Product (MSP) Register.

LSP Register Clock. The rising edge of CLKL loads the Least Significant Product (LSP) Register.

THE FOLLOWING PIN DESCRIPTIONS APPLY TO THE HMU17 ONLY

CLK

ENX

ENY

ENP

Clock. The rising edge of this clock will load all enabled registers.

X-Register Enable. When ENX is LOW, the X-register is enabled; X-input data and TCX will be

latched at the rising edge of CLK. When ENX is high, the X-register is in a hold mode.

Y-Register Enable. ENY enables the Y-register. (See ENX).

Product Register Enable. ENP enables the Product Register. Both the MSP and LSP

Sections are enabled by ENP. (See ENX).

HMU16GC-45 Related Products

	HMU16GC-45	HMU16JC-35	HMU16JC-45	HMU16	HMU17	HMU17JC-45	HMU17GC-45	HMU17JC-35	HMU17GC-35	HMU16GC-35
Description	16-BIT, DSP-MULTIPLIER, CPGA68	16-BIT, DSP-MULTIPLIER, CPGA68	16-BIT, DSP-MULTIPLIER, CPGA68	16-BIT, DSP-MULTIPLIER, CPGA68	16-BIT, DSP-MULTIPLIER, CPGA68	16-BIT, DSP-MULTIPLIER, CPGA68	16-BIT, DSP-MULTIPLIER, CPGA68	16-BIT, DSP-MULTIPLIER, PQCC68	16-BIT, DSP-MULTIPLIER, CPGA68	16-BIT, DSP-MULTIPLIER, CPGA68

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