Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
F
EATURES
• 9 single ended LVCMOS/LVTTL outputs;
(8) clocks, (1) feedback
• PCLK, nPCLK pair can accept the following differential
input levels: LVPECL, CML, SSTL
• Maximum output frequency: PLL Mode, 175MHz
• VCO range: 250MHz to 700MHz
• Output skew: 75ps (maximum)
• Cycle-to-cycle jitter: 50ps (maximum)
• Static phase offset: 90ps ± 110ps
• 3.3V supply voltage
G
ENERAL
D
ESCRIPTION
The ICS86953I-147 is a low voltage, low skew
1-to-9 Differential-to-LVCMOS/LVTTL Clock
HiPerClockS™
Generator and a member of the HiPerClock ™
S
family of High Performance Clock Solutions from
ICS. The PCLK, nPCLK pair can accept most stan-
dard differential input levels. With output frequencies up to 175MHz,
the ICS86953I-147 is targeted for high performance clock ap-
plications. Along with a fully integrated PLL, the ICS86953I-147
contains frequency configurable outputs and an external feed-
back input for regenerating clocks with “zero delay”.
ICS
P
IN
A
SSIGNMENT
VCO_SEL
nBYPASS
PLL_SEL
GND
GND
V
DDO
QFB
Q0
• -40°C to 85°C ambient operating temperature
• Pin compatible to the MPC953
32 31 30 29 28 27 26 25
V
DDA
FB_CLK
nc
nc
nc
nc
GND
PCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
nPCLK
MR/nOE
V
DDO
Q7
GND
Q6
V
DDO
Q5
24
23
22
Q1
V
DDO
Q2
GND
Q3
V
DDO
Q4
GND
ICS86953I-147
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
B
LOCK
D
IAGRAM
PCLK
nPCLK
FB_CLK
VCO_SEL
nBYPASS
MR/nOE
PLL_SEL
0
Phase
Detector
0
LPF
VCO
1
÷2
1
÷4
0
1
7
QFB
/
Q0:Q6
Q7
86953BYI-147
www.icst.com/products/hiperclocks.html
1
REV. B APRIL 23, 2004
Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
Type
Power
Input
Unused
Power
Input
Input
Pullup
Pullup
Description
Analog supply pin.
Feedback clock input. LVCMOS / LVTTL interface levels.
No connect.
Power supply ground.
Non-inver ting LVPECL differential clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4, 5, 6
7, 13, 17,
21, 25, 29
8
9
Name
V
DDA
FB_CLK
nc
GND
PCLK
nPCLK
Pullup/ Inver ting LVPECL differential clock input.
Pulldown Internally biased to V
DDO
/2.
Active HIGH Master Reset. Active LOW output enable. When
logic High, the internal dividers are reset and the outputs are
10
MR/nOE
Input
Pulldown
tri-stated (HiZ). When logic LOW, the internal dividers and
the outputs are enabled. LVCMOS / LVTTL interface levels.
Power
Output supply pins.
11, 15, 19, 23, 27
V
DDO
12, 14, 16, 18,
Q7, Q6, Q5, Q4,
Clock outputs. LVCMOS / LVTTL interface levels.
Output
20, 22, 24, 26
Q3, Q2, Q1, Q0
14
Ω
typical output impedance.
Feedback clock output. LVCMOS / LVTTL interface levels.
28
QFB
Output
14
Ω
typical output impedance.
Selects VCO when HIGH. When LOW, selects PCLK,
30
P LL_S E L
Input
Pullup
nPCLK. LVCMOS / LVTTL interface levels.
31
nBYPASS
Input
Pullup
Selects PLL when HIGH. When LOW, in Bypass mode.
Selects VCO ÷2 when HIGH. Selects VCO ÷1 when LOW.
32
VCO_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
P D
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance (per output)
Output Impedance
V
DDA
, V
DDO
= 3.465V
5
Test Conditions
Minimum Typical
4
51
51
7
14
12
Maximum
Units
pF
KΩ
KΩ
pF
Ω
T
ABLE
3A. O
UTPUT
C
ONTROL
P
IN
F
UNCTION
T
ABLE
Input
MR/nOE
1
0
Outputs
QFB, Q0:Q7
HiZ
Enabled
T
ABLE
3B. P
ROGRAMMABLE
O
UTPUT
F
REQUENCY
F
UNCTION
T
ABLE
Inputs
Bypass
0
1
1
1
1
86953BYI-147
PLL_SEL
X
0
0
1
1
VCO_SEL
X
0
1
0
1
Operation
Test Mode: PLL and divider bypass
Test Mode: PLL bypass
Test Mode: PLL bypass
PLL Mode
PLL Mode
Outputs
QFB, Q0:Q7
CLK
CLK/4
CLK/8
VCO/4
VCO/8
REV. B APRIL 23, 2004
www.icst.com/products/hiperclocks.html
2
Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DDA
V
DDO
I
DDA
I
DDO
Parameter
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
20
75
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
Parameter
Input
High Voltage
Input
Low Voltage
Input Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
I
OH
= -20mA
I
OL
= 20mA
V
DD
- 0.6
0.6
VCO_SEL, nBYPASS,
PLL_SEL, MR/nOE
FB_CLK
VCO_SEL, nBYPASS,
PLL_SEL, MR/nOE
FB_CLK
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
±120
Units
V
V
V
V
µA
V
V
V
IL
I
IN
V
OH
V
OL
NOTE: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "3.3V Output Load Test Circuit".
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IN
V
PP
Parameter
Input Current
Peak-to-Peak Input Voltage
0.15
Test Conditions
Minimum
Typical
Maximum
±120
1.3
V
DD
- 0.85
Units
µA
V
V
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
V
CMR
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications
,
the maximum input voltage for PCLK, nPCLK is V
DD
+ 0.3V.
86953BYI-147
www.icst.com/products/hiperclocks.html
3
REV. B APRIL 23, 2004
Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
Test Conditions
Minimum
Typical
Maximum
175
Units
MHz
T
ABLE
5. PLL I
NPUT
R
EFERENCE
C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
REF
Parameter
Input Reference Frequency
T
ABLE
6. AC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
PLL Mode
Output Frequency
Propagation Delay;
NOTE 1
PLL Mode
Bypass Mode
PCLK, nPCLK
Measured on rising edge
at V
DD
/2
-20
20% to 80%
100
47
50
90
2.5
Test Conditions
VCO_SEL = 1
VCO_SEL = 0
Minimum
31.25
62.50
Typical
Maximum
87.5
175
200
4
75
50
200
700
53
10
6
Units
MHz
MHz
MHz
ns
ps
ps
ps
ps
%
ms
ns
ns
t
sk(o)
t
jitter(cc)
t(Ø)
t
R
/ t
F
odc
t
LOCK
t
EN
Output Skew; NOTE 2, 4
Cycle-to-Cycle Jitter; NOTE 5
Static Phase Offset; NOTE 3, 5
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
7
t
DIS
NOTE: Termination of 50
Ω
to V
DD
/2.
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
86953BYI-147
www.icst.com/products/hiperclocks.html
4
REV. B APRIL 23, 2004
Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V±5%
V
DD
V
DDA
,
V
DDO
SCOPE
nPCLK
Qx
V
PP
LVCMOS
GND
Cross Points
V
CMR
PCLK
GND
-1.65V±5%
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
V
V
D
IFFERENTIAL
I
NPUT
L
EVEL
V
DDO
DDO
DDO
Q0:Q7,
QFB
➤
Clock
Outputs
20%
2
2
2
DDO
Qx
2
t
cycle
n
➤
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
C
YCLE
-
TO
-C
YCLE
J
ITTER
80%
t
R
O
UTPUT
R
ISE
/F
ALL
T
IME
V
Q0:Q7
QFB
Pulse Width
t
PERIOD
odc =
t
PW
t
PERIOD
➤
t
(Ø)
tjit(Ø)
=
t
(Ø) —
t
(Ø)
mean
= Phase Jitter
(where
t
(Ø) is any random sample, and
t
(Ø)
mean
is the average
of the sampled cycles measured on controlled edges)
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
86953BYI-147
P
HASE
J
ITTER
& S
TATIC
P
HASE
O
FFSET
REV. B APRIL 23, 2004
www.icst.com/products/hiperclocks.html
5
➤
➤
DDO
t
cycle n+1
➤
V
DDO
Qy
2
t
sk(o)
O
UTPUT
S
KEW
nPCLK
80%
PCLK
20%
t
F
Q0:Q7,
QFB
V
DDO
2
t
PD
P
ROPAGATION
D
ELAY
nPCLK
2
V
OH
V
OL
V
OH
V
DDO
PCLK
FB_CLK
V
OL
2
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