70V3599S166BC8 datasheet, PDF - EEWORLD Datasheet

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70V3599S166BC8: DescriptionSRAM 128Kx36 STD-PWR 3.3V SYNC DUAL-PORT RAM; Categorystorage storage; File Size248KB，23 Pages; ManufacturerIDT (Integrated Device Technology)

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70V3599S166BC8 Overview

SRAM 128Kx36 STD-PWR 3.3V SYNC DUAL-PORT RAM

70V3599S166BC8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	CABGA
package instruction	LBGA, BGA256,16X16,40
Contacts	256
Manufacturer packaging code	BC256
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Samacsys Description	CHIP ARRAY BGA 17.0 X 1.7.0 MM X 1.0 MM
Maximum access time	12 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	S-PBGA-B256
JESD-609 code	e0
length	17 mm
memory density	4718592 bit
Memory IC Type	DUAL-PORT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	256
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum standby current	0.03 A
Minimum standby current	3.15 V
Maximum slew rate	0.5 mA
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	17 mm

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HIGH-SPEED 3.3V

128/64K x 36

SYNCHRONOUS

IDT70V3599/89S

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (12Gbps bandwidth)

– Fast 3.6ns clock to data out

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output mode

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz.

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B B

WWW

2 3 3

L L R

B B

1 0

R R

1 /0

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

1d 0d

1c 0c 1b 0b 1a 0a

a b cd

0a 1a 0b 1b

0c 1c 0d 1d

0/1

FT/PIPE

0/1

FT/PIPE

d cba

128K x 36

MEMORY

ARRAY

I/O

- I/O

35 L

Din_L

Din_R

I/O

- I/O

35R

CLK

16L (1)

REPEAT

ADS

CNTEN

CLK

16R

(1)

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

5617 tbl 01

TDI

NOTE:

1. A

is a NC for IDT70V3589.

JTAG

TDO

TCK

TMS

TRST

OCTOBER 2014

DSC 5617/10

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