CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Limiting input current to 100A is recommended to avoid latchup problems. Typically 1mA is safe, however this is not guaranteed.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Input Offset Voltage
(Note 3)
V
SUPPLY
=
5V.
See Test Circuit, Unless Otherwise Specified
SYMBOL
V
OS
V
OS
/T
V
OS
/T
I
BIAS
I
OS
R
IN
A
VOL
V
OUT
CMVR
CMVR = -5V to +3.5V
V
S
=
3V
to
8V
R
S
= 100,
f = DC to 10Hz
f = 10Hz
C
L
= 50pF, R
L
= 10k
R
L
= 10k, V
O
=
4V
R
L
= 10k
R
L
= 100k
TEST CONDITIONS
TEMP.
(°C)
+25
0 to +70
0 to +70
+25
+25
0 to +70
+25
0 to +70
+25
+25
0 to +70
+25
+25
+25
0 to +70
+25
0 to +70
PSRR
e
N
i
N
GBWP
SR
t
R
OS
V+ to V-
I
SUPP
No Load
+25
+25
+25
+25
+25
+25
+25
+25
+25
0 to +70
MIN
-
-
-
-
-
-
-
-
-
135
130
4.7
-
-5
-5
120
120
120
-
-
-
-
-
-
4.5
-
-
TYP
0.7
1
0.02
100
4
5
8
10
10
12
150
-
4.85
4.95
-5.2 to +4
-
140
-
140
2
0.01
2
2.5
0.2
20
-
2
-
MAX
5
8
-
-
10
20
20
40
-
-
-
-
-
3.5
3.5
-
-
-
-
-
-
-
-
-
16
3
3.2
UNITS
V
V
V/°C
nV/month
pA
pA
pA
pA
dB
dB
V
V
V
V
dB
dB
dB
V
P-P
pA/Hz
MHz
V/s
s
%
V
mA
mA
Average Temperature Coefficient of
Input Offset Voltage
(Note 3)
Change in Input Offset with Time
Input Bias Current
|I(+)|, |I(-)|
Input Offset Current
|I(-), |I(+)|
Input Resistance
Large Signal Voltage Gain
(Note 3)
Output Voltage Swing (Note 4)
Common Mode Voltage Range
(Note 3)
Common Mode Rejection Ratio
(Note 3)
Power Supply Rejection Ratio
Input Noise Voltage
Input Noise Current
Gain Bandwidth Product
Slew Rate
Rise Time
Overshoot
Operating Supply Range
Supply Current
CMRR
FN2920 Rev 10.00
April 12, 2007
Page 3 of 13
ICL7650S
Electrical Specifications
PARAMETER
Output Source Current
Output Sink Current
Internal Chopping Frequency
Clamp ON Current (Note 5)
Clamp OFF Current
(Note 5)
NOTES:
3. These parameters are guaranteed by design and characterization, but not tested at temperature extremes because thermocouple effects prevent
precise measurement of these voltages in automatic test equipment.
4. OUTPUT CLAMP not connected. See typical characteristic curves for output swing vs clamp current characteristics.
5. See OUTPUT CLAMP under detailed description.
6. All significant improvements over the industry-standard ICL7650 are highlighted in
bold italics.
V
SUPPLY
=
5V.
See Test Circuit, Unless Otherwise Specified
(Continued)
SYMBOL
I
O SOURCE
I
O SINK
f
CH
Pins 13 and 14 Open
R
L
= 100k
-4V
V
OUT
+4V
TEST CONDITIONS
TEMP.
(°C)
+25
0 to +70
+25
0 to +70
+25
+25
+25
0 to +70
MIN
2.9
2.3
25
20
120
25
-
-
TYP
4.5
-
30
-
250
70
0.001
-
MAX
-
-
-
-
375
-
5
10
UNITS
mA
mA
mA
mA
Hz
A
nA
nA
Test Circuit
R
2
1M
R
1
1M
INTERMODULATION
Previous chopper-stabilized amplifiers have suffered from
intermodulation effects between the chopper frequency and
input signals. These arise because the finite AC gain of the
amplifier necessitates a small AC signal at the input. This is
seen by the zeroing circuit as an error signal, which is
chopped and fed back, thus injecting sum and difference
frequencies and causing disturbances to the gain and phase
vs frequency characteristics near the chopping frequency.
These effects are substantially reduced in the ICL7650S by
feeding the nulling circuit with a dynamic current,
corresponding to the compensation capacitor current, in such
a way as to cancel that portion of the input signal due to finite
AC gain. Since that is the major error contribution to the
ICL7650S, the intermodulation and gain/phase disturbances
are held to very low values, and can generally be ignored.
CAPACITOR CONNECTION
The null/storage capacitors should be connected to the
CEXTA and CEXTB pins, with a common connection to the
CRETN pin. This connection should be made directly by
either a separate wire or PC trace to avoid injecting load
current IR drops into the capacitive circuitry. The outside foil,
where available, should be connected to CRETN.
OUTPUT CLAMP
The OUTPUT CLAMP pin allows reduction of the overload
recovery time inherent with chopper-stabilized amplifiers.
When tied to the inverting input pin, or summing junction, a
current path between this point and the OUTPUT pin occurs
just before the device output saturates. Thus uncontrolled
input differentials are avoided, together with the consequent
charge buildup on the correction-storage capacitors. The
output swing is slightly reduced.
-
ICL7650S
+
C
0.1F
C
R
C
OUTPUT
0.1F
Application Information
Detailed Description
AMPLIFIER
The functional diagram shows the major elements of the
ICL7650S. There are two amplifiers, the main amplifier, and the
nulling amplifier. Both have offset-null capability. The main
amplifier is connected continuously from the input to the output,
while the nulling amplifier, under the control of the chopping
oscillator and clock circuit, alternately nulls itself and the main
amplifier. The nulling connections, which are MOSFET gates,
are inherently high impedance, and two external capacitors
provide the required storage of the nulling potentials and the
necessary nulling-loop time constants. The nulling arrangement
operates over the full common-mode and power-supply
ranges, and is also independent of the output level, thus giving
exceptionally high CMRR, PSRR, and A
VOL
.
Careful balancing of the input switches, and the inherent
balance of the input circuit, minimizes chopper frequency
charge injection at the input terminals, and also the feed
forward-type injection into the compensation capacitor, which
is the main cause of output spikes in this type of circuit.
FN2920 Rev 10.00
April 12, 2007
Page 4 of 13
ICL7650S
CLOCK
The ICL7650S has an internal oscillator, giving a chopping
frequency of 200Hz, available at the CLOCK OUT pin on the 14
pin devices. Provision has also been made for the use of an
external clock in these parts. The INT/EXT pin has an internal
pull-up and may be left open for normal operation, but to utilize
an external clock this pin must be tied to V- to disable the
internal clock. The external clock signal may then be applied to
the EXT CLOCK IN pin. An internal divide-by-two provides the
desired 50% input switching duty cycle. Since the capacitors
are charged only when EXT CLOCK IN is high, a 50% to 80%
positive duty cycle is recommended, especially for higher
frequencies. The external clock can swing between V+ and V-.
The logic threshold will be at about 2.5V below V+. Note also
that a signal of about 400 Hz, with a 70% duty cycle, will be
present at the EXT CLOCK IN pin with INT/EXT high or open.
This is the internal clock signal before being fed to the divider.
In those applications where a strobe signal is available, an
alternate approach to avoid capacitor misbalancing during
overload can be used. If a strobe signal is connected to EXT
CLK IN so that it is low during the time that the overload
signal is applied to the amplifier, neither capacitor will be
charged. Since the leakage at the capacitor pins is quite low
at room temperature, the typical amplifier will drift less than
10V/s, and relatively long measurements can be made with
little change in offset.
COMPONENT SELECTION
The two required capacitors, C
EXTA
and C
EXTB
, have
optimum values depending on the clock or chopping
frequency. For the preset internal clock, the correct value is
0.1F, and to maintain the same relationship between the
chopping frequency and the nulling time constant this value
should be scaled approximately in proportion if an external
clock is used. A high quality film type capacitor such as
mylar is preferred, although a ceramic or other lower-grade
capacitor may prove suitable in many applications. For
quickest settling on initial turn-on, low dielectric absorption
capacitors (such as polypropylene) should be used. With
ceramic capacitors, several seconds may be required to
settle to 1V.
STATIC PROTECTION
All device pins are static-protected by the use of input diodes.
However, strong static fields and discharges should be avoided,
as they can cause degraded diode junction characteristics,
which may result in increased input-leakage currents.
LATCHUP AVOIDANCE
Junction-isolated CMOS circuits inherently include a parasitic
4-layer (PNPN) structure which has characteristics similar to
an SCR. Under certain circumstances this junction may be
triggered into a low-impedance state, resulting in excessive
supply current. To avoid this condition, no voltage greater than
0.3V beyond the supply rails should be applied to any pin. In
general, the amplifier supplies must be established either at
the same time or before any input signals are applied. If this is
not possible, the drive circuits must limit input current flow to
under 1mA to avoid latchup, even under fault conditions.
OUTPUT STAGE/LOAD DRIVING
The output circuit is a high-impedance type (approximately
18k), and therefore with loads less than this value, the
chopper amplifier behaves in some ways like a
transconductance amplifier whose open-loop gain is
proportional to load resistance. For example, the open-loop
gain will be 17dB lower with a 1k load than with a 10k
load. If the amplifier is used strictly for DC, this lower gain is
of little consequence, since the DC gain is typically greater
than 120dB even with a 1k load. However, for wideband
applications, the best frequency response will be achieved
with a load resistor of 10k or higher. This will result in a
smooth 6dB/octave response from 0.1Hz to 2MHz, with
phase shifts of less than 10° in the transition region where
the main amplifier takes over from the null amplifier.
THERMO-ELECTRIC EFFECTS
The ultimate limitations to ultra-high precision DC amplifiers are
the thermo-electric or Peltier effects arising in thermocouple
junctions of dissimilar metals, alloys, silicon, etc. Unless all
junctions are at the same temperature, thermoelectric voltages
typically around 0.1V/°C, but up to tens of mV/°C for some
materials, will be generated. In order to realize the extremely
low offset voltages that the chopper amplifier can provide, it is
essential to take special precautions to avoid temperature
gradients. All components should be enclosed to eliminate air
movement, especially that caused by power-dissipating
elements in the system. Low thermoelectric-efficient
connections should be used where possible and power supply
voltages and power dissipation should be kept to a minimum.
High-impedance loads are preferable, and good separation
from surrounding heat-dissipating elements is advisable.
GUARDING
Extra care must be taken in the assembly of printed circuit
boards to take full advantage of the low input currents of the
ICL7650S. Boards must be thoroughly cleaned with TCE or
alcohol and blown dry with compressed air. After cleaning,
the boards should be coated with epoxy or silicone rubber to
prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble, particularly since the input pins
are adjacent to pins that are at supply potentials. This
leakage can be significantly reduced by using guarding to
lower the voltage difference between the inputs and adjacent
metal runs. The guard, which is a conductive ring
surrounding the inputs, is connected to a low impedance
point that is at approximately the same voltage as the inputs.
Leakage currents from high-voltage pins are then absorbed
京公网安备 11010802033920号
EEWORLD
