IS41C4405
X
IS41LV4405
X
S
ERIES
4M x 4 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
• Fast Page Mode Access Cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
-- 4,096 cycles/64 ms
• Refresh Mode:
RAS-Only,
CAS-before-RAS
(CBR), and Hidden
• Single power supply:
5V±10% or 3.3V ± 10%
• Byte Write and Byte Read operation via two
CAS
• Industrial temperature range -40°C to 85°C
ISSI
JUNE 2001
DESCRIPTION
®
The
ISSI
4405x Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. The Fast
Page Mode allows 2,048 or 4096 random accesses within
a single row with access cycle time as short as 20 ns per
4-bit word.
These features make the 4405x Series ideally suited for
high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The 4405x Series is packaged in a 24-pin 300-mil SOJ
with JEDEC standard pinouts.
PRODUCT SERIES OVERVIEW
Part No.
IS41C44052
IS41C44054
IS41LV44052
IS41LV44054
Refresh
2K
4K
2K
4K
Voltage
5V ± 10%
5V ± 10%
3.3V ± 10%
3.3V ± 10%
KEY TIMING PARAMETERS
Parameter
RAS
Access Time (t
RAC
)
CAS
Access Time (t
CAC
)
Column Address Access Time (t
AA
)
Fast Page Mode Cycle Time (t
PC
)
Read/Write Cycle Time (t
RC
)
-50
50
13
25
20
84
-60
60
15
30
25
104
Unit
ns
ns
ns
ns
ns
PIN CONFIGURATION
24 (26) Pin SOJ
PIN DESCRIPTIONS
A0-A11
VCC
I/O0
I/O1
WE
RAS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
Address Inputs (4K Refresh)
Address Inputs (2K Refresh)
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
A0-A10
I/O0-3
WE
OE
RAS
CAS
Vcc
GND
NC
*A11(NC)
A10
A0
A1
A2
A3
VCC
* A11 is NC for 2K Refresh devices.
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
06/24/01
1
IS41C4405
X
IS41LV4405
X
S
ERIES
FUNCTIONAL BLOCK DIAGRAM
ISSI
®
OE
WE
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
OE
CAS
CAS
WE
RAS
RAS
CLOCK
GENERATOR
DATA I/O BUS
REFRESH
COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS
SENSE AMPLIFIERS
I/O0-I/O3
MEMORY ARRAY
4,194,304 x 4
ADDRESS
BUFFERS
A0-A10(A11)
TRUTH TABLE
Function
Standby
Read
Write: Word (Early Write)
Read-Write
Hidden Refresh
Read
Write
(1)
RAS
H
L
L
L
L→H→L
L→H→L
H→L
H→L
CAS
H
L
L
L
L
L
H
L
WE
X
H
L
H→L
H
L
X
X
OE
X
L
X
L→H
L
X
X
X
Address t
R
/t
C
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
High-Z
D
OUT
D
IN
D
OUT
, D
IN
D
OUT
D
OUT
High-Z
High-Z
RAS-Only
Refresh
CBR Refresh
Note:
1. EARLY WRITE only.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
06/24/01
IS41C4405
X
IS41LV4405
X
S
ERIES
Functional Description
The IS41C4405x and IS41LV4405x are CMOS DRAMs
optimized for high-speed bandwidth, low power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 11 or 12 address bits. These are
entered 11 bits (A0-A10) at a time for the 2K refresh
device or 12 bits (A0-A11) at a time for the 4K refresh
device. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS).
RAS
is used to latch the
first nine bits and
CAS
is used the latter ten bits.
ISSI
Auto Refresh Cycle
®
To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in each
64ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) or 4096 row addresses (A0 through A11) with
RAS at least once every 32 ms or 64ms respectively.
Any read, write, read-modify-write or RAS-only cycle
refreshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-RAS
refresh is activated by the falling edge of
RAS,
while
holding
CAS
LOW. In
CAS-before-RAS
refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles containing
a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time speci-
fied by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
,
t
CAC
and t
OEA
are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE,
whichever
occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
06/24/01
3
IS41C4405
X
IS41LV4405
X
S
ERIES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Commercial Operation Temperature
Industrial Operation Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
–1.0 to +7.0
–0.5 to +4.6
–1.0 to +7.0
–0.5 to +4.6
50
1
0 to +70
-40 to +85
–55 to +125
Unit
V
V
mA
W
°C
°C
ISSI
®
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
V
CC
V
IH
V
IL
T
A
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Commercial Ambient Temperature
Industrial Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Min.
4.5
3.0
2.4
2.0
–1.0
–0.3
0
-40
Typ.
5.0
3.3
—
—
—
—
—
—
Max.
5.5
3.6
V
CC
+ 1.0
V
CC
+ 0.3
0.8
0.8
70
85
Unit
V
V
V
°C
°C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A10(A11)
Input Capacitance:
RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O3
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
06/24/01
IS41C4405
X
IS41LV4405
X
S
ERIES
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
I
IL
I
IO
V
OH
V
OL
I
CC
1
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Test Condition
Any input 0V
≤
V
IN
≤
Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V
≤
V
OUT
≤
Vcc
I
OH
= –5.0 mA, Vcc = 5V
I
OH
= –2.0 mA, Vcc = 3.3V
I
OL
= 4.2 mA, Vcc = 5V
I
OL
= 2 mA, Vcc = 3.3V
RAS, CAS
≥
V
IH
Commercial
Industrial
I
CC
2
I
CC
3
Standby Current: CMOS
Operating Current:
Random Read/Write
(2,3)
Average Power Supply Current
Operating Current:
Fast Page Mode
(2,3,4)
Average Power Supply Current
Refresh Current:
RAS-Only
(2,3)
Average Power Supply Current
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
RAS, CAS
≥
V
CC
– 0.2V
RAS, CAS,
Address Cycling, t
RC
= t
RC
(min.)
RAS=
V
IL
,
CAS
≥
V
IH
t
RC
= t
RC
(min.)
RAS
Cycling,
CAS
≥
V
IH
t
RC
= t
RC
(min.)
RAS, CAS
Cycling
t
RC
= t
RC
(min.)
5V
3.3V
5V
3.3V
5V
3.3V
—
-50
-60
-50
-60
-50
-60
-50
-60
V
CC
Speed
Min.
–5
–5
2.4
—
ISSI
Max.
5
5
—
0.4
2
0.5
3
2
1
120
110
90
80
120
110
120
110
Unit
µA
µA
V
V
mA
®
—
—
—
—
0.5
—
—
—
—
—
—
—
—
mA
mA
I
CC
4
mA
I
CC
4
mA
I
CC
5
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
RAS
refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast Page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
06/24/01
5
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