L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
DESCRIPTION
The
L8C201, L8C202, L8C203,
and
L8C204
are dual-port First-In/First-
Out (FIFO) memories. The FIFO
memory products are organized as:
L8C201 — 512 x 9-bit
L8C202 — 1024 x 9-bit
L8C203 — 2048 x 9-bit
L8C204 — 4096 x 9-bit
Each device utilizes a special algorithm
that loads and empties data on a first-
in/first-out basis. Full and Empty flags
are provided to prevent data overflow
and underflow. Three additional pins
are also provided to allow for unlimited
expansion in both word size and depth.
Depth Expansion does not result in a
flow-through penalty. Multiple devices
are connected with the data and control
signals in parallel. The active device is
determined by the Expansion In (XI)
and Expansion Out (XO) signals which
are daisy chained from device to
device.
The read and write operations are
internally sequential through the use
of ring pointers. No address informa-
tion is required to load and unload
data. The write operation occurs
when the Write (W) signal is LOW.
Read occurs when Read (R) goes
LOW. The nine data outputs go to the
high impedance state when R is
HIGH. Retransmit (RT) capability
allows for reset of the read pointer
when RT is pulsed LOW, allowing for
retransmission of data from the
beginning. Read Enable (R) and Write
Enable (W) must both be HIGH
during a retransmit cycle, and then R
is used to access the data. A Half-Full
(HF) output flag is available in the
single device and width expansion
modes. In the depth expansion
configuration, this pin provides the
Expansion Out (XO) information
which is used to tell the next FIFO that
it will be activated.
These FIFOs are designed to have the
fastest data access possible. Even in
lower cycle time applications, faster
access time can eliminate timing
bottlenecks as well as leave enough
margin to allow the use of the devices
without external bus drivers.
READ
POINTER
FEATURES
u
First-In/First-Out (FIFO) using
Dual-Port Memory
u
Advanced CMOS Technology
u
High Speed — to 10 ns Access Time
u
Asynchronous and Simultaneous
Read and Write
u
Fully Expandable by both Word
Depth and/or Bit Width
u
u
u
u
Empty and Full Warning Flags
Half-Full Flag Capability
Auto Retransmit Capability
Package Styles Available:
• 28-pin Plastic DIP
• 32-pin Plastic LCC
• 28-pin Ceramic Flatpack
L8C201/202/203/204 B
LOCK
D
IAGRAM
DATA INPUTS
D
8-0
9
W
WRITE
CONTROL
RAM ARRAY
512 x 9-bit
1K x 9-bit
2K x 9-bit
4K x 9-bit
WRITE
POINTER
The FIFOs are designed for those
applications requiring asychronous
and simultaneous read/writes in
multiprocessing and rate buffer
applications.
THREE-STATE
BUFFERS
R
READ
CONTROL
DATA OUTPUTS
Q
8-0
RS
FL/RT
RESET
LOGIC
FLAG
LOGIC
EF
FF
XI
EXPANSION
LOGIC
XO/HF
FIFO Products
1
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
“final” read cycle but inhibiting
further read operations with the data
outputs remaining in a high imped-
ance state. Once a valid write operat-
ing has been accomplished, the Empty
Flag (EF) will go HIGH after
tWHEH
and a valid read can then begin.
When the FIFO is empty, the internal
read pointer is blocked from R so
external changes in R will not affect
the FIFO.
FL/RT — First Load/Retransmit
Outputs
FF — Full Flag
The Full Flag (FF) will go LOW,
inhibiting further write operations,
indicating that the device is full. If the
read pointer is not moved after Reset
(RS), the Full Flag (FF) will go LOW
after 512 writes for the
L8C201,
1024
writes for the
L8C202,
2048 writes for
the
L8C203,
and 4096 writes for the
L8C204.
EF — Empty Flag
SIGNAL DEFINITIONS
Inputs
RS — Reset
Reset is accomplished whenever the
Reset (RS) input is taken to a LOW
state. During reset, both internal read
and write pointers are set to the first
location. A reset is required after
power-up before a write operation can
take place. Both the Read Enable (R)
and Write Enable (W) inputs must be
in the HIGH state during the window
shown (i.e.,
tWHSH
before the rising
edge of RS) and should not change
until
tSHWL
after the rising edge of
RS. Hall-Full Flag (HF) will be reset to
high after Reset (RS).
W — Write Enable
A write cycle is initiated on the falling
edge of this input if the Full Flag (FF)
is not set. Data setup and hold time
must be adhered to with respect to the
rising edge of the Write Enable (W).
Data is stored in the RAM array
sequentially and independently of any
on-going read operation.
To prevent data overflow, the Full
Flag (FF) will go LOW, inhibiting
further write operations. Upon the
completion of a valid read operation,
the Full Flag (FF) will go HIGH after
tRHFH,
allowing a valid write to
begin. When the FIFO is full, the
internal write pointer is blocked from
W, so external changes in W will not
affect the FIFO when it is full.
R — Read Enable
This is a dual-purpose input. In the
Depth Expansion Mode, this pin is
grounded to indicate that it is the first
loaded (see Operating Modes). In the
Single Device Mode, this pin acts as
the retransmit input. The Single
Device Mode is initiated by grounding
the Expansion In (XI).
The FIFOs can be made to retransmit
data when the Retransmit Enable
control (RT) input is pulsed LOW. A
retransmit operation will set the
internal read pointer to the first location
and will not affect the write pointer.
Read Enable (R) and Write Enable (W)
must be in the HIGH state during
retransmit. This feature is useful when
less than the full memory has been
written between resets. Retransmit will
affect the Half-Full Flag (HF), depend-
ing on the relative locations of the read
and write pointers. The retransmit
feature is not compatible with the
Depth Expansion Mode.
XI — Expansion In
This input is a dual-purpose pin.
Expansion In (XI) is grounded to
indicate an operation in the single
device mode. Expansion In (XI) is
connected to Expansion Out (XO) of
the previous device in the Depth
Expansion or Daisy Chain Mode.
D
8-0
— Data Input
Data input signals for 9-bit wide data.
Data has setup and hold time require-
ments with respect to the rising edge
of W.
BS
O
2
A read cycle is initiated on the falling
edge of the Read Enable (R) provided
the Empty Flag (EF) is not set. The
data is accessed on a First-In/First-
Out basis, independent of any ongo-
ing write operation. After Read
Enable (R) goes HIGH, the Data
Outputs (D
8-0
) will return to a high
impedance condition until the next
read operation. When all the data has
been read from the FIFO, the Empty
Flag (EF) will go LOW, allowing the
O
LE
TE
Q
8-0
— Data Output
The Empty Flag (EF) will go LOW,
inhibiting further read operations,
when the read pointer is equal to the
write pointer, indicating that the
device is empty.
XO/HF — Expansion Out/Half-Full Flag
This is a dual-purpose output. In the
Single Device Mode, when Expansion
In (XI) is grounded, this output acts as
an indication of a half-full memory.
After half of the memory is filled and
at the falling edge of the next write
operation, the Half-Full Flag (HF) will
be set to LOW and will remain set
until the difference between the write
pointer and read pointer is less than or
equal to one-half of the total memory
of the device. The Half-Full Flag (HF)
is then deasserted by the rising edge
of the read operation.
In the Depth Expansion Mode,
Expansion In (XI) is connected to
Expansion Out (XO) of the previous
device. This output acts as a signal to
the next device in the daisy chain by
providing a pulse to the next device
when the previous device reaches the
last location of memory.
Data outputs for 9-bit wide data. This
data is in a high impedance condition
whenever Read Enable (R) is in a
HIGH state or the device is empty.
FIFO Products
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
4. External logic is needed to generate
a composite Full Flag (FF) and
Empty Flag (EF). This requires the
ORing of all EFs and ORing of all
FFs (i.e., all must be set to generate
the correct composite FF or EF).
5. The Retransmit (RT) function and
Half-Full Flag (HF) are not avail-
able in the Depth Expansion Mode.
Bidirectional Mode
OPERATING MODES
Single Device Mode
A single FIFO may be used when the
application requirements are for the
number of words in a single device.
The FIFOs are in a Single Device
Configuration when the Expansion In
(XI) control input is grounded. In this
mode the Half-Full Flag (HF), which is
an active-low output, is the active
function of the combination pin XO/
HF.
1. The first device must be designated
by grounding the First Load (FL)
control input.
O
2. All other devices must have FL in
the HIGH state.
3. The Expansion Out (XO) pin of
each device must be tied to the
Expansion In (XI) pin of the next
device with the last device connect-
ing back to the first.
BS
FIFO Products
3
03/04/99–LDS.8C201/2/3/4-H
The FIFOs can easily be adapted to
applications where the requirements
are for greater than the number of
words in a single device. Any depth
can be attained by adding additional
FIFOs. The FIFOs operates in the
Depth Expansion configuration when
the following conditions are met:
O
Depth Expansion (Daisy Chain) Mode
LE
Applications which require data
buffering between two systems (each
system capable of read and write
Width Expansion Mode
operations) can be achieved by pairing
Word width may be increased simply FIFOs. Care must be taken to assure
by connecting the corresponding input that the appropriate flag is monitored
control signals of multiple devices.
by each system (i.e., FF is monitored
Status flags (EF, FF, and HF) can be
on the device when W is used; EF is
detected from any one device. Any
monitored on the device when R is
word width can be attained by adding used). Both Depth Expansion and
additional FIFOs. Flag detection is
Width Expansion may be used in this
accomplished by monitoring the FF,
mode.
EF, and HF signals on either (any)
device used in the width expansion
configuration.
Do not connect any
output signals together.
TE
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
V
CC
supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –0.5 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 5)
Symbol
V
OH
V
OL
V
IH
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Test Condition
LE
40
90
30
95
25
100
20
110
4
TE
Min
2.4
Typ
2.0
–0.5
L8C201/202/203/204-
15
120
12
150
Mode
Active Operation, Commercial
Active Operation, Industrial
Active Operation, Military
Temperature Range
(Ambient)
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
Supply Voltage
4.5 V
≤
V
CC
≤
5.5 V
4.5 V
≤
V
CC
≤
5.5 V
4.5 V
≤
V
CC
≤
5.5 V
L8C201/202/203/204
Max Unit
V
0.4
V
CC
+0.3
0.8
V
V
V
CC
= 4.5 V,
I
OH
= –2.0 mA
V
CC
= 4.5 V,
I
OL
= 8.0 mA
V
IL
I
IX
I
OZ
I
CC2
I
CC3
C
IN
C
OUT
Input Low Voltage
Input Leakage Current
Output Leakage Current
O
(Note 3)
V
µA
µA
mA
mA
pF
pF
Ground
≤
V
IN
≤
V
CC
±1
±10
15
5
5
7
V
CC
Current, TTL Inactive
V
CC
Current, CMOS Standby
Input Capacitance
Output Capacitance
O
Symbol
I
CC1
Parameter
BS
R
≥
V
IH
, GND
≤
V
OUT
≤
V
CC
All Inputs =
V
IH
MIN
(Note 6)
All Inputs =
V
CC
(Note 12)
Ambient Temp = 25°C,
V
CC
= 4.5 V
Test Frequency = 1 MHz
(Note 9)
Test Condition
(Note 5)
10
180
Unit
mA
V
CC
Current, Active
FIFO Products
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS
Over Commercial and Industrial Operating Range
A
SYNCHRONOUS AND
R
ESET
T
IMING
(ns)
L8C201/202/203/204–
25
Symbol
t
RLRL
t
RLQV
t
RHRL
t
RLRH
t
RHQV
t
RHQZ
t
WLWL
t
WLWH
t
WHWL
t
DVWH
t
WHDX
t
SLSH
t
SLWL
t
WHSH
t
RHSH
t
SHWL
t
SLEL
t
SLHH
t
SLFH
Parameter
Read Cycle Time
(MHz)
Read Low to Output Valid
(Access Time)
Read High to Read Low
(Notes 8, 9)
Read Low to End of Read Cycle
(Notes 8, 9)
Read High to Output Valid
Read High to Output High Z
(Note 14)
Write Cycle Time
(Note 9)
Write Low to Write High
(Notes 8, 9)
Write High to End of Write Cycle
(Notes 8, 9)
Data Valid to Write High
(Notes 8, 9)
Write High to Data Change
(Notes 8, 9)
Reset Cycle Time
(Notes 9, 10)
Reset Low to Write Low
(Notes 9, 10)
Write High to Reset High
(Notes 9, 10)
Read High to Reset High
(Notes 9, 10)
Reset High to Write Low
(Notes 9, 10)
Reset Low to Empty Flag Low
Reset Low to Half-Full Flag High
Reset Low to Full Flag High
10
25
5
20
Min
35
25
10
15
5
15
Max
15
Min
25
15
8
12
5
15
Max
Min
20
12
5
10
5
15
15
10
5
8
0
10
15
10
10
5
12
12
12
10
10
10
12
Max
10
Min
15
10
Max
LE
35
25
25
10
25
25
25
t
RLRL
t
RHRL
t
RLRH
t
RLQV
t
RHQZ
DATA-OUT VALID
A
SYNCHRONOUS
R
EAD
R
AND
W
RITE
O
PERATION
t
RLQV
BS
Q
8-0
W
D
8-0
O
t
RHQV
DATA-OUT VALID
t
WLWL
t
WLWH
t
WHWL
t
WHDX
DATA-IN VALID
t
DVWH
DATA-IN VALID
R
ESET
T
IMING
O
t
SLWL
t
SLSH
t
WHSH
t
SHWL
RS
W
t
RHSH
R
t
SLEL
EF
t
SLHH
, t
SLFH
HF, FF
5
TE
35
25
10
15
0
25
15
10
10
0
20
12
8
8
0
25
15
25
15
15
10
15
15
15
12
20
12
12
8
FIFO Products
03/04/99–LDS.8C201/2/3/4-H
DSP and ARM Processors
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