A40MX02-1PL44 datasheet, PDF - EEWORLD Datasheet

A40MX02-1PL44: DescriptionFPGA - Field Programmable Gate Array MX; CategoryProgrammable logic devices Programmable logic; File Size7MB，142 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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FPGA - Field Programmable Gate Array MX

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microsemi
Parts packaging code	LCC
package instruction	PLASTIC, LCC-44
Contacts	44
Reach Compliance Code	unknown
Other features	ALSO OPERATES AT 5V SUPPLY
maximum clock frequency	92 MHz
Combined latency of CLB-Max	2.3 ns
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
length	16.5862 mm
Humidity sensitivity level	3
Configurable number of logic blocks	295
Equivalent number of gates	3000
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
organize	295 CLBS, 3000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	16.5862 mm

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