DATASHEET
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
9EX21801A
Description
The
9EX21801
provides 18 output clocks for PCIe Gen2
(100MHz) or QPI (133MHz) applications. The
9EX21801
has 4
selectable SMBus addresses, and dedicated CKPWRGD/PD#
and VDDA pins for easy board design. A differential CPU clock
from a CK410B+ main clock generator, such as the
932S421,
drives the
9EX21801.
In fanout mode, the
9EX21801
provides
outputs up to 400MHz.
Features/Benefits
•
•
•
•
•
Supports output clock frequencies up to 400 MHz
4 Selectable SMBus addresses
SMBus address is independent of PLL operating mode
Dedicated CKPWRGD/PD# and VDDA pins ease board
design
Available in industrial temperature range (-40°C to +85°C)
Key Specifications
•
•
•
•
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 150 ps
PCIe Gen2 compliant phase noise
QPI 133MHz compliant phase noise
Functional Block Diagram
OE(17:15)#
OE(14:5)#,
OE_01234#
12
CLKA_IN
CLKA_IN#
CLKB_IN
CLKB_IN#
PLL
(SS Compatible)
18
DIF(17:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0
SMB_A1
SEL_A_B#
SMBDAT
SMBCLK
Logic
IREF
IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
1463E — 07/20/11
1
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
Datasheet
HIBW_BYPM_LOBW#
Pin Configuration
CKPWRGD/PD#
100M_133M#
SEL_A_B#
SMBDAT
SMBCLK
SMB_A0
SMB_A1
DIF_9#
DIF_8#
DIF_7#
DIF_9
DIF_8
DIF_7
OE9#
OE8#
OE7#
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDD
OE10#
DIF_10
DIF_10#
OE11#
DIF_11
DIF_11#
OE12#
DIF_12
DIF_12#
GND
VDD
DIF_13
DIF_13#
OE13#
DIF_14
DIF_14#
OE14#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DIF_15
DIF_15#
VDD
OE15_17#
DIF_16
DIF_16#
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
CLKA_IN#
GND
CLKB_IN
CLKB_IN#
VDD
OE_01234#
DIF_6#
DIF_6
OE6#
DIF_5#
DIF_5
OE5#
DIF_4#
DIF_4
DIF_3#
DIF_3
GND
VDD
DIF_2#
DIF_2
DIF_1#
DIF_1
DIF_0#
DIF_0
9EX21801AKLF
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
DIF_17
DIF_17#
IREF
GNDA
VDDA
CLKA_IN
72-pin MLF
Frequency/Functionality Table
Byte 0,
bit 2
(100_133M#
Latch)
1
0
0
0
0
1
1
1
Power Groups
Byte 0,
bit 1
FSB
0
0
1
1
0
0
1
1
Byte 0,
bit 0
FSA
1
1
1
0
0
0
0
1
Input
MHz
100.00
133.33
166.67
200.00
266.67
333.33
400.00
DIF_x
MHz
100.00
133.33
166.67
200.00
266.67
333.33
400.00
Reserved
Notes
1
1
2
2
2
2
2
Pin Number
VDD
GND
29
28
1,12,21,35,43,55 11,32,44
VDD
Description
Main PLL, Analog
DIF clocks
Power Down Functionality
INPUTS
CKPWRGD/PD#
Input
1
Running
0
X
OUTPUTS
DIF_x
Running
Hi-Z
PLL State
ON
OFF
Notes:100M_133M#
1. Latch selects between 100 and 133 MHz.
This is equivalent to FSC in CK410B+/CK509B FS table.
2. Writing Byte 0 bits (2:0) can select other frequencies.
These frequencies are not characterized in PLL Mode
SMBus Address Selection (pins 66, 67)
SMB_A1
0
0
1
1
SMB_A0
0
1
0
1
Address
D4
D6
D8
DA
HIBW_BYPM_LOBW# Selection (Pin 63)
State
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.0V
Mode
Low BW
Bypass
High BW
IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
1463E — 07/20/11
2
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
Datasheet
Pin Description
PIN #
PIN NAME
1
VDD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
OE10#
DIF_10
DIF_10#
OE11#
DIF_11
DIF_11#
OE12#
DIF_12
DIF_12#
GND
VDD
DIF_13
DIF_13#
OE13#
DIF_14
DIF_14#
OE14#
DIF_15
DIF_15#
VDD
OE15_17#
DIF_16
DIF_16#
DIF_17
DIF_17#
IREF
GNDA
VDDA
CLKA_IN
CLKA_IN#
GND
CLKB_IN
CLKB_IN#
VDD
OE_01234#
PIN TYPE
DESCRIPTION
PWR
Power supply, nominal 3.3V
Active low input for enabling DIF pair 10.
IN
1 = tri-state outputs, 0 = enable outputs
OUT
0.7V differential true clock output
OUT
0.7V differential complement clock output
Active low input for enabling DIF pair 11.
IN
1 = tri-state outputs, 0 = enable outputs
OUT
0.7V differential true clock output
OUT
0.7V differential complement clock output
Active low input for enabling DIF pair 12.
IN
1 = tri-state outputs, 0 = enable outputs
OUT
0.7V differential true clock output
OUT
0.7V differential complement clock output
PWR
Ground pin.
PWR
Power supply, nominal 3.3V
OUT
0.7V differential true clock output
OUT
0.7V differential complement clock output
Active low input for enabling DIF pair 13.
IN
1 = tri-state outputs, 0 = enable outputs
OUT
0.7V differential true clock output
OUT
0.7V differential complement clock output
Active low input for enabling DIF pair 14.
IN
1 = tri-state outputs, 0 = enable outputs
OUT
0.7V differential true clock output
OUT
0.7V differential complement clock output
PWR
Power supply, nominal 3.3V
Active low input for enabling DIF pairs 15, 16 and 17
IN
1 = tri-state outputs, 0 = enable outputs
OUT
0.7V differential true clock output
OUT
0.7V differential complement clock output
OUT
0.7V differential true clock output
OUT
0.7V differential complement clock output
This pin establishes the reference current for the differential current-mode output pairs. This pin
OUT
requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475
ohms is the standard value.
PWR
Ground pin for the PLL core.
PWR
3.3V power for the PLL core.
IN
True Input for differential reference clock.
IN
Complement Input for differential reference clock.
PWR
Ground pin.
IN
True Input for differential reference clock.
IN
Complement Input for differential reference clock.
PWR
Power supply, nominal 3.3V
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
IN
1 = tri-state outputs, 0 = enable outputs
IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
1463E — 07/20/11
3
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
Datasheet
Pin Description (continued)
PIN #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN NAME
DIF_0
DIF_0#
DIF_1
DIF_1#
DIF_2
DIF_2#
VDD
GND
DIF_3
DIF_3#
DIF_4
DIF_4#
OE5#
DIF_5
DIF_5#
OE6#
DIF_6
DIF_6#
VDD
OE7#
DIF_7
DIF_7#
OE8#
DIF_8
DIF_8#
100M_133M#
HIBW_BYPM_LOBW#
SMBCLK
SMBDAT
SMB_A1
SMB_A0
SEL_A_B#
CKPWRGD/PD#
DIF_9
DIF_9#
OE9#
PIN TYPE
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
IN
IN
I/O
IN
IN
IN
IN
OUT
OUT
IN
DESCRIPTION
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Input to select operating frequency. See Frequency/Functionality Table for functionality of this
pin.
Trilevel input to select High BW, Bypass Mode or Low BW.
0 = Low BW Mode, Mid= Bypass Mode, 1 = High Bandwidth
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
SMBus address bit 1
SMBus address bit 0 (LSB)
Input to select differential input clock A or differential input clock B.
0 = Input B selected, 1 = Input A selected.
Notifies the clock to sample latched inputs on the rising edge, and to power down on the falling
edge.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
1463E — 07/20/11
4
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
Datasheet
MIN
-0.5
-0.5
-65
0
-40
2000
TYP
MAX
4.6
4.6
150
70
85
115
UNITS
V
V
°
C
°C
°C
°C
V
Notes
1
1
1
1
1
1
1
Absolute Maximum Ratings
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Supply
Voltage
Storage Temperature
Ambient Operating Temp
C ase Temperature
Input ESD protection
SYMBOL
VDDA
VDD
Ts
T
C OM
T
IND
Tcase
ESD prot
CONDITIONS
Analog PLL Supply, referenced to GND
Main power supply , referenced to GND
Human Body Model
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= T
C OM
or T
IND
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Digital Supply Current
Analog Supply Current
Digital Powerdown
C urrent
Analog Powerdown
C urrent
Input Frequency
Pin Inductance
Capacitance
SYMBOL
V
IH
V
IL
I
IH
I
IL1
I
IL2
I
DD 3.3D
I
D D3.3 A
I
DD 3.3D PD
I
DD 3.3APD
F
iPL L
F
iPL L
F
iBYPASS
L
pin
C
IN
C
OUT
T
ST AB
f
MOD
t
LAT OE#
t
D RVPD
t
F
t
R
CONDITIONS
3.3 V +/-5%, referenced to GND
3.3 V +/-5%, referenced to GND
V
IN
= V
DD
V
IN
= 0 V; Inputs w/o pull-up resistors
V
IN
= 0 V; Inputs w/ pull-up resistors
VDD, Full Active, C
L
= Full load;
VDDA, Full Active, C
L
= Full load;
all differential pairs tri-stated
all differential pairs tri-stated
100MHz PLL Mode
133MHz PLL Mode
Bypass Mode
Logic Inputs
Output pin capacitance
From V
DD
Power-Up and after input
clock stabilization or de-assertion of PD#
to 1st clock
Triangular Modulation
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD de-assertion
Fall time of OE#
Rise time of OE#
80
90
33
1.5
MIN
2
-0.3
-5
-5
-200
TYP
MAX
3.6
0.8
5
UNITS NOTES
V
V
uA
uA
uA
mA
mA
mA
mA
MHz
MHz
MHz
nH
pF
pF
ms
kHz
cycles
us
ns
ns
1
1
1
1
1
1
1
1
1
1
1
1,3
1,2
1,2
1
450
40
15
20
110
150
400
7
5
6
1
30
4
33
12
300
5
5
Clk Stabilization
Allowable Spread
Modulation Frequency
OE# Latency
Tdrive_PD
Tfall
Trise
1
2
Guaranteed by design and characterization, not 100% tested in production.
Time from deassertion until outputs are >200 mV
3
For w hich spread spectrum tracking error spec will be met.
IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
1463E — 07/20/11
5
京公网安备 11010802033920号
EEWORLD
