SI5351B-B-GMR datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > semiconductor> Analog mixed-signal IC> SI5351B-B-GMR

SI5351B-B-GMR: DescriptionClock Generators & Support Products Any-Rate, Dual PLL 1 60MHz Clock 8outputs; Categorysemiconductor Analog mixed-signal IC; File Size2MB，41 Pages; ManufacturerSilicon Laboratories; Environmental Compliance

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SI5351B-B-GMR Overview

Clock Generators & Support Products Any-Rate, Dual PLL 1 60MHz Clock 8outputs

SI5351B-B-GMR Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	Clock Generators & Support Products
RoHS	Details
Type	Programmable Clock Generators
Maximum Input Frequency	27 MHz
Max Output Freq	160 MHz
Number of Outputs	8 Output
Duty Cycle - Max	55 %
Operating Supply Voltage	3.3 V
Operating Supply Current	27 mA
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	QFN-20
Packaging	Cut Tape
Packaging	MouseReel
Packaging	Reel
Output Type	CMOS
Jitter	35 ps
Moisture Sensitive	Yes
Factory Pack Quantity	2500
Unit Weight	0.001498 oz

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Si5351A/B/C-B

C - P

R O G R A M M A B L E

-F

R E Q U E N C Y

C M O S C

LO CK

EN ER ATO R

+ V C X O

Features



www.silabs.com/custom-timing



Generates up to 8 non-integer-related

frequencies from 2.5 kHz to 200 MHz



C user definable configuration

Exact frequency synthesis at each output



(0 ppm error)

Highly linear VCXO



Optional clock input (CLKIN)

Low output period jitter: < 70 ps pp, typ



Configurable spread spectrum selectable



at each output

Operates from a low-cost, fixed frequency



crystal: 25 or 27 MHz



Supports static phase offset

Programmable rise/fall time control

Glitchless frequency changes

Separate voltage supply pins provide

level translation:



Core VDD: 2.5 or 3.3 V



Output VDDO: 1.8, 2.5, or 3.3 V

Excellent PSRR eliminates external

power supply filtering

Very low power consumption

Adjustable output delay

Available in 2 packages types:

10-MSOP: 3 outputs

20-QFN (4x4 mm): 8 outputs

PCIE Gen 1 compatible

Supports HCSL compatible swing

10-MSOP

20-QFN

Applications



Ordering Information:

See page 29

HDTV, DVD/Blu-ray, set-top box



Audio/video equipment, gaming



Printers, scanners, projectors



Handheld Instrumentation



Residential gateways



Networking/communication



Servers, storage



XO replacement

Description

The Si5351 is an I

C configurable clock generator that is ideally suited for replacing

crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in

cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional

divider architecture, the Si5351 can generate any frequency up to 200 MHz on each of its

outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide

variety of applications. The Si5351A generates up to 8 free-running clocks using an

internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an

internal VCXO and provides the flexibility to replace both free-running clocks and

synchronous clocks. It eliminates the need for higher cost, custom pullable crystals while

providing reliable operation over a wide tuning range. The Si5351C offers the same

flexibility but synchronizes to an external reference clock (CLKIN).

Functional Block Diagram

Si5351B (20-QFN)

OSC

VCXO

PLL

MultiSynth

VDDOA

CLK0

CLK1

VDDOB

CLK2

CLK3

VDDOC

CLK4

CLK5

VDDOD

CLK6

CLK7

SDA

SCL

INTR

OEB

Control

Logic

CLKIN

OSC

Si5351C (20-QFN)

PLL

MultiSynth

VDDOA

CLK0

CLK1

VDDOB

CLK2

CLK3

VDDOC

CLK4

CLK5

VDDOD

CLK6

CLK7

SDA

SCL

OEB

SSEN

Control

Logic

Rev. 1.0 4/15

Si5351A/B/C-B

Si5351A/B/C-B

ABLE O F

ONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.4. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5. Control Pins (OEB, SSEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5. Configuring the Si5351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1. Writing a Custom Configuration to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2. Si5351 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3. Replacing Crystals and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.4. Replacing Crystals, Crystal Oscillators, and VCXOs . . . . . . . . . . . . . . . . . . . . . . . .20

5.5. Replacing Crystals, Crystal Oscillators, and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.6. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.7. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6.1. Power Supply Decoupling/Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.3. External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6.4. External Crystal Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.5. Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6.6. Trace Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7. Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

9. Si5351 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.1. Si5351A 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

9.2. Si5351B 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

9.3. Si5351C 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.4. Si5351A 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

11. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

11.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

12. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

12.1. 10-Pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

13. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

14.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

14.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Rev. 1.0

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