Synchronous Ethernet Two-Channel
PLL for 10GbE and 40GbE
FEATURES
HIGHLIGHTS
•
•
•
•
•
•
•
•
Jitter generation <0.3 ps RMS (10 kHz to 20 MHz), meets jitter
requirements of leading PHYs supporting 10GBASE-R, 10GBASE-
W, 40GBASE-R, OC-192 and STM-64
Supports ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE)
compliant equipment
Supports clock generation for IEEE-1588 applications
Generates SyncE interface clocks (1GE, 10GE, and 40GE)
Provides an integrated solution for reference switching, frequency
translation and jitter attenuation for SyncE and SONET/SDH inter-
faces
Integrates 2 DPLLs, one for the transmit path and one for the
receive path
Selectable DPLL bandwidth: 18 Hz and 35 Hz
Integrates 2 jitter attenuating APLLs to generate ultra-low jitter
clocks
•
Supports 3 clock modes: SONET, Ethernet, and Ethernet LAN-
PHY
•
Supports up to two crystal connections, allowing each APLL to
support up to two modes of operation
Supports input and output clocks covering a wide range of frequen-
cies
•
Provides IN3, IN4, IN7,IN6 input CMOS clocks whose frequen-
cies range from 2 kHz to 156.25 MHz
•
Provides IN1 and IN2 input differential clocks whose frequencies
range from 2 kHz to 625 MHz
•
Provides OUT1 to OUT5 output CMOS clocks whose frequency
range from 1PPS to 125 MHz
•
Provides OUT6~OUT9 output differential clocks whose fre-
quency range from 25 MHz to 644.53125 MHz
Provides a 1PPS, 2 kHz, 4 kHz, or 8 kHz frame sync input signal,
and a 1PPS, 2 kHz or 8 kHz frame sync output signal
•
•
•
•
•
•
•
IDT82V3911
Short Form
Datasheet
MAIN FEATURES
Supports Forced or Automatic operating mode switch controlled by
an internal state machine. Automatic mode switch supports Free-
Run, Locked and Holdover modes
Supports manual and automatic selected input clock switch
Supports automatic hitless selected input clock switch on clock fail-
ure
Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
Supports LVPECL/LVDS and CMOS input/output technologies
Supports master clock calibration
Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,
ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recom-
mendations
I2C Microprocessor interface
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 V operation with 5 V tolerant CMOS I/Os
1mm ball pitch CABGA green package
Core and access IP switches / routers
Gigabit and Terabit IP switches / routers
Central Office Timing Source and Distribution
DWDM cross-connect and transmission equipment
IP core routers and access equipment
Cellular and WLL base-station node clocks
Broadband and multi-service access equipment
OTHER FEATURES
•
•
•
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
2013
Integrated Device Technology, Inc.
July 1, 2013
DSC-7238/-
IDT82V3911 SHORT FORM DATASHEET
SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE
DESCRIPTION
The 82V3911 Synchronous Ethernet (SyncE) Two-channel PLL is a
jitter attenuating device with rate conversion and reference switching
capabilities; its ultra-low jitter output clocks are used to directly synchro-
nize 10GBASE-R/10GBASE-W and OC-192/STM-64 PHYs and
40GBASE-R PHYs in Synchronous Ethernet and SONET/SDH equip-
ment. When the 82V3911 is locked to a Synchronous Equipment Timing
Source (SETS) that meets the requirements of ITU-T G.8262, G.813 or
Telcordia GR-253-CORE Stratum 3 or SONET Minimum Clock the
clocks generated by the 82V3911 will also meet those requirements.
The two 82V3911 timing channels are defined by independent Digital
PLLs (DPLLs) with embedded clock synthesizers. The two independent
timing channels allow the 82V3911 to synchronize transmit interfaces
with the selected system backplane clock, and to simultaneously provide
a recovered clock from a selected receive interface to the system back-
plane. DPLL1 is preferred for synchronizing transmit interfaces because
it has the more sophisticated holdover mode.
Both DPLLs support three primary operating modes: Free-Run,
Locked and Holdover. In Free-Run mode the DPLLs generate clocks
based on the master clock alone. In Locked mode the DPLLs filter refer-
ence clock jitter with one of the following selectable bandwidths: 18 Hz
or 35 Hz. In Locked mode the long-term DPLL frequency accuracy is the
same as the long term frequency accuracy of the selected input refer-
ence. In Holdover mode the DPLL uses frequency data acquired while in
Locked mode to generate accurate frequencies when input references
are not available.
The 82V3911 requires a 12.8 MHz master clock for its reference
monitors and other digital circuitry. The frequency accuracy of the mas-
ter clock determines the frequency accuracy of the DPLLs in Free-Run
mode. The frequency stability of the master clock determines the fre-
quency stability of the DPLLs in Free-Run mode and in Holdover mode.
The 82V3911 provides four single ended reference inputs and two
differential reference inputs that can operate at common Ethernet,
SONET/SDH and PDH frequencies and other frequencies. The refer-
ences are continually monitored for loss of signal and for frequency off-
set per user programmed thresholds. All of the references are available
to both DPLLs. The active reference for each DPLL is determined by
forced selection or by automatic selection based on user programmed
priorities and locking allowances and based on the reference monitors.
The 82V3911 can accept a clock reference and a phase locked
external sync signal as a pair. DPLL1 can lock to the reference clock
input and align its frame sync and multi-frame sync outputs with the
paired external sync input. The device provides to two external sync
inputs that can be associated with any of the six reference inputs to cre-
ate up to two pairs. The external sync signals can have a frequency of 1
Hz, 2 kHz or 8 kHz. This feature enables DPLL1 to phase align its frame
sync and multi-frame sync outputs with an external sync input without
the need use a low bandwidth setting to lock directly to an external sync
input.
The clocks synthesized by the 82V3911 DPLLs can be passed
through either of the two independent voltage controlled crystal oscillator
(VCXO) based jitter attenuating analog PLLs (APLLs). Both APLLs drive
two independent dividers that have differential outputs. The APLLs use
external crystal resonators with resonant frequencies equal to the APLL
base frequency divided by 25. Both APLLs can be provisioned with one
or two selectable crystal resonators to support up to two base frequen-
cies per APLL. The output clocks generated by the APLLs exhibit jitter
below 0.30ps RMS over the integration range 10 kHz to 20 MHz for most
output frequencies.
Description
2
July 1, 2013
IDT82V3911 SHORT FORM DATASHEET
SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE
FUNCTIONAL BLOCK DIAGRAM
GSM/OBSAI/16E1/
16T1
ETH
Auto
Divider
Auto
Divider
FRSYNC_8K_1PPS
Input
Selector
DPLL1
16E1/16T1
MFRSYNC_2K_1PPS
12E1/GPS/E3/T3
Input
77.76MHz
OUT1
MUX
Divider
OUT1
Diff
IN1
IN2
IN3
IN4
IN5
IN6
Input Pre-Divider
Input Pre-Divider
Input Pre-Divider
Input Pre-Divider
Input Pre-Divider
Input Pre-Divider
Priority
Priority
Priority
Priority
Priority
Priority
GSM/GPS/16E1/
16T1
SONET/GETH
Monitors
OUT2
MUX
Divider
OUT2
SE
OUT3
MUX
Divider
OUT3
SE
ETH
EX_SYNC1
EX_SYNC2
Selection
Input
Selector
DPLL2
16E1/16T1
OUT4
MUX
Divider
OUT4
12E1/24T1/E3/T3
77.76MHz
OUT5
MUX
From DPLL1
Divider
OUT5
OUT6
Microprocessor Interface
SONET/GETH
Divider
APLL1
MUX
APLL1
Divider
From DPLL2
IN_APLL1
OUT7
Diff
JTAG
From DPLL1
Divider
APLL2
APLL2
Divider
OUT8
System Clock
IN_APLL2
From DPLL2
MUX
OUT9
OSCI
Crystal
Crystal
Figure 1. Functional Block Diagram
Functional Block Diagram
3
July 1, 2013
IDT82V3911 DATASHEET
SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE
1
PIN ASSIGNMENT
1
A
IC10
2
VDDA
3
XTAL1_IN
4
CAP1
5
IN_APLL1_N
EG
6
NC
7
NC
8
TDI
9
IC7
10
NC
11
OSCI
12
TMS
13
IC6
14
TRST
A
B
IC11
VSSA
XTAL1_OUT
VSSAO
IN_APLL1_P
OS
NC
NC
TDO/
DPLL1_
LOS_lNT
VSSAO
TCK
VSSA
VSSA
VSSDO
VDDDO
B
C
IC4
VDDA
NC
CAP2
MFRSYNC_2 FRSYNC_8K_
K_1PPS
1PPS
VDDDO
VSSDO
VDDA
VSSA
VDDA
VDDA
INT_REQ
NC
C
D
VSSA
VSSAO
CAP3
VSSA
VDDA
NC
VSSD
VDDD
IC2
VDDA
VSSA
VDDA
OUT4
OUT5
D
E
XTAL3_IN
XTAL3_OUT
VSSA
VSSAO
VSSA
SONET/SDH
VSSD
VDDD
IC1
VSSA
VDDA
VSSA
OUT2
OUT3
E
F
VDDD
VSSD
VSSAO
VSSA
VDDA
VSSAO
VSSD
VDDD
VSSD
VDDD
EX_SYNC1
VDDDO
OUT1
VSSDO
F
G
C
on
fid
en
tia
l
VSSD
VDDD
VSSAO
VSSAO
VSSAO
VSSD
VDDD
IC3
VDDD
VSSD
EX_SYNC2
NC
NC
NC
G
H
VDDAO
VSSAO
VDDAO
VSSAO
VSSAO
VSSAO
VSSD
VDDD
VSSD
VDDD
NC
NC
RST
IN3
H
J
OUT6_NEG
OUT6_POS
VDDAO
VSSAO
VDDAO
VSSAO
VDDAO
VSSAO
VSSA
VDDA
DPLL1_
LOCK
NC
IN4
IN5
J
T
VSSAO
VSSAO
VSSAO
VDDAO
VSSAO
VDDAO
ID
K
VSSAO
VSSD
VDDD
VSSAO
DPLL2_
LOCK
IN6
I2C_SCL
I2C_SDA
K
L
OUT7_NEG
OUT7_POS
VDDAO
VSSAO
VSSAO
VSSAO
VSSAO
I2C_AD1
I2C_AD2
CAP4
VSSA
CAP5
VSSA
CAP6
L
M
VDDAO
VSSAO
VSSAO
VSSAO
VDDAO
VSSAO
VDDAO
VSSAO
VSSAO
VSSAO
VSSAO
NC
XTAL4_OUT
XTAL4_IN
M
N
VSSAO
OUT8_POS
VSSAO
OUT9_POS
VSSAO
IN_APLL2_P
OS
IN1_POS
IN2_POS
VSSA
XTAL2_OUT
VSSA
IC9
VSSAO
VSSA
N
P
VDDAO
OUT8_NEG
VSSAO
OUT9_NEG
VDDAO
IN_APLL2_N
EG
IN1_NEG
IN2_NEG
VDDA
XTAL2_IN
VDDA
IC8
IC5
VDDA
P
1
Key:
Diff
Outputs
2
Outputs
3
Inputs
4
Power
5
Ground
6
7
8
9
10
11
12
13
14
Figure 2. Pin Assignment (Top View)
Pin Assignment
4
July 1, 2013
IDT82V3911 SHORT FORM DATASHEET
SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE
2
Name
PIN DESCRIPTION
Pin No.
I/O
Type
Global Control Signal
OSCI
A11
I
CMOS
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2,
INPUT_MODE_CNFG):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the
device will still be held in reset state for 500 ms (typical).
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
EX_SYNC2: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
Input Clock
IN1_POS / IN1_NEG: Positive / Negative Input Clock 1
A
2 kHz, 4 kHz,
N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
LVPECL/LVDS 125MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz, 312.5 MHz, 622.08 MHz or 625 MHz
clock is differentially input on this pair of pins. Whether the clock signal is LVPECL or
LVDS is automatically detected.
Single-ended input for differential input is also supported. Refer to
Chapter 7.3.2.5 Sin-
gle-Ended Input for Differential Input.
IN2_POS / IN2_NEG: Positive / Negative Input Clock 2
A
2 kHz, 4 kHz,
N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
LVPECL/LVDS 125MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz or 312.5 MHz, 622.08 MHz or 625 MHz
clock is differentially input on this pair of pins. Whether the clock signal is LVPECL or
LVDS is automatically detected.
Single-ended input for differential input is also supported. Refer to
Chapter 7.3.2.5 Sin-
gle-Ended Input for Differential Input.
IN3: Input Clock 3
A
2 kHz, 4 kHz,
N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
CMOS
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
IN4: Input Clock 4
A
2 kHz, 4 kHz,
N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
CMOS
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
IN5: Input Clock 5
A
2 kHz, 4 kHz,
N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
CMOS
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
Description
1
Table 1: Pin Description
SONET/SDH
E6
I
pull-down
CMOS
RST
H13
I
pull-up
CMOS
Frame Synchronization Input Signal
EX_SYNC1
EX_SYNC2
F11
G11
I
pull-down
I
pull-down
CMOS
CMOS
IN1_POS
IN1_NEG
N7
I
P7
IN2_POS
IN2_NEG
N8
I
P8
IN3
H14
I
pull-down
IN4
J13
I
pull-down
IN5
J14
I
pull-down
Pin Description
5
July 1, 2013
RF/Wirelessly
京公网安备 11010802033920号
EEWORLD
