74LVT573D-T datasheet, PDF - EEWORLD Datasheet

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74LVT573D-T: DescriptionLatches 3.3V OCTAL D TRANS LATCH 3-S; Categorylogic logic; File Size912KB，17 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVT573D-T Overview

Latches 3.3V OCTAL D TRANS LATCH 3-S

74LVT573D-T Parametric

Parameter Name	Attribute value
Source Url Status Check Date	2013-06-14 00:00:00
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOIC
package instruction	SOP, SOP20,.25
Contacts	20
Reach Compliance Code	unknown
Other features	BROADSIDE VERSION OF 373
series	LVT
JESD-30 code	R-PDSO-G20
JESD-609 code	e4
length	12.8 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.064 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Maximum supply current (ICC)	12 mA
Prop。Delay @ Nom-Sup	4.3 ns
propagation delay (tpd)	5.2 ns
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	BICMOS
Temperature level	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm
Base Number Matches	1

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74LVT573

3.3 V octal D-type transparent latch; 3-state

Rev. 8 — 22 November 2011

Product data sheet

1. General description

The 74LVT573 is a high-performance BiCMOS product designed for V

operation at

3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The

two sections of the device are controlled independently by Latch Enable (LE) and Output

Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to

facilitate PC board layout and allow easy interface with microprocessors.

The data on the Dn inputs are transferred to the latch outputs when the Latch Enable (LE)

input is High. The latch remains transparent to the data inputs while LE is High, and stores

the data that is present one setup time before the High-to-Low enable transition.

The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS

memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all

eight 3-state buffers independent of the latch operation.

When OE is Low, the latched or transparent data appears at the outputs. When OE is

High, the outputs are in the High-impedance “OFF” state, which means they will neither

drive nor load the bus.

2. Features and benefits



Inputs and outputs arranged for easy interfacing to microprocessors

3-state outputs for bus interfacing

Common output enable control

TTL input and output switching levels

Input and output interface capability to systems at 5 V supply

Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

Live insertion and extraction permitted

No bus current loading when output is tied to 5 V bus

Power-up reset

Power-up 3-state

Latch-up protection



JESD78 class II exceeds 500 mA



ESD protection:



HBM JESD22-A114E exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



Specified from

40 C

to +85

C

74LVT573D-T Related Products

	74LVT573D-T	CMF20200K00JNEK80	74LVT573D
Description	Latches 3.3V OCTAL D TRANS LATCH 3-S	Fixed Resistor, Metal Film, 1W, 200000ohm, 500V, 5% +/-Tol, 200ppm/Cel,	Latches 3.3V OCTAL D TRANS LATCH 3-S
Is it Rohs certified?	conform to	conform to	conform to
Reach Compliance Code	unknown	compliant	unknown
series	LVT	CMF INDUSTRIAL	LVT
JESD-609 code	e4	e3	e4
Number of terminals	20	2	20
Maximum operating temperature	85 °C	175 °C	85 °C
Minimum operating temperature	-40 °C	-55 °C	-40 °C
Package shape	RECTANGULAR	TUBULAR PACKAGE	RECTANGULAR
Package form	SMALL OUTLINE	Axial	SMALL OUTLINE
technology	BICMOS	METAL FILM	BICMOS
Terminal surface	NICKEL PALLADIUM GOLD	Matte Tin (Sn)	NICKEL PALLADIUM GOLD
Maker	NXP	-	NXP
Parts packaging code	SOIC	-	SOIC
package instruction	SOP, SOP20,.25	-	PLASTIC, SO-20
Contacts	20	-	20
Other features	BROADSIDE VERSION OF 373	-	BROADSIDE VERSION OF 373
JESD-30 code	R-PDSO-G20	-	R-PDSO-G20
length	12.8 mm	-	12.8 mm
Load capacitance (CL)	50 pF	-	50 pF
Logic integrated circuit type	BUS DRIVER	-	BUS DRIVER
MaximumI(ol)	0.064 A	-	0.032 A
Humidity sensitivity level	1	-	1
Number of digits	8	-	8
Number of functions	1	-	1
Number of ports	2	-	2
Output characteristics	3-STATE	-	3-STATE
Output polarity	TRUE	-	TRUE
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	SOP	-	SOP
Encapsulate equivalent code	SOP20,.25	-	SOP20,.4
method of packing	TAPE AND REEL	Bulk	-
Peak Reflow Temperature (Celsius)	260	-	260
power supply	3.3 V	-	3.3 V
Maximum supply current (ICC)	12 mA	-	12 mA
Prop。Delay @ Nom-Sup	4.3 ns	-	4.3 ns
propagation delay (tpd)	5.2 ns	-	5.2 ns
Certification status	Not Qualified	-	Not Qualified
Maximum seat height	2.65 mm	-	2.65 mm
Maximum supply voltage (Vsup)	3.6 V	-	3.6 V
Minimum supply voltage (Vsup)	2.7 V	-	2.7 V
Nominal supply voltage (Vsup)	3.3 V	-	3.3 V
surface mount	YES	-	YES
Temperature level	INDUSTRIAL	-	INDUSTRIAL
Terminal form	GULL WING	-	GULL WING
Terminal pitch	1.27 mm	-	1.27 mm
Terminal location	DUAL	-	DUAL
Maximum time at peak reflow temperature	30	-	30
width	7.5 mm	-	7.5 mm
Base Number Matches	1	-	1

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