Features
•
Incorporates the ARM926EJ-S™ ARM
®
Thumb
®
Processor
– DSP Instruction Extensions
– ARM Jazelle
®
Technology for Java
®
Acceleration
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 210 MIPS at 190 MHz
– Memory Management Unit
– EmbeddedICE
™
, Debug Communication Channel Support
– Mid-level implementation Embedded Trace Macrocell
™
Additional Embedded Memories
– 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed
– 16 Kbytes of Internal SRAM, Single-cycle Access at Bus Speed
External Bus Interface (EBI)
– Supports SDRAM, Static Memory, NAND Flash and CompactFlash
®
LCD Controller
– Supports Passive or Active Displays
– Up to 16-bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048
USB
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
• Dual On-chip Transceivers
• Integrated FIFOs and Dedicated DMA Channels
– USB 2.0 Full Speed (12 Mbits per second) Device Port
• On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs
Bus Matrix
– Handles Five Masters and Five Slaves
– Boot Mode Select Option
– Remap Command
Fully Featured System Controller (SYSC) for Efficient System Management, including
– Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a
Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
– Three 32-bit PIO Controllers
Reset Controller (RSTC)
– Based on Power-on Reset Cells, Reset Source Identification and Reset Output
Control
Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
Clock Generator (CKGR)
– 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a
Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator and two PLLs
Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
Capabilities
– Four Programmable External Clock Signals
•
•
•
AT91 ARM
Thumb-based
Microcontrollers
AT91SAM9261S
•
•
Summary
•
•
•
•
•
6242ES–ATARM–11-Sep-09
•
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention
– Mode for General Purpose Two-wire UART Serial Communication
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock
Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock
Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
Nineteen Peripheral DMA (PDC) Channels
Multimedia Card Interface (MCI)
– SDCard and MultiMediaCard
™
Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant
Three Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA
®
Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support
Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel EEPROMs Supported
IEEE
®
1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies:
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC and for VDDPLL
– 2.7V to 3.6V for VDDIOP (Peripheral I/Os)
– 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os)
Available in a 217-ball LFBGA RoHS-compliant Package
•
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2
AT91SAM9261S
6242ES–ATARM–11-Sep-09
AT91SAM9261S
1. Description
The AT91SAM9261S is a complete system-on-chip built around the ARM926EJ-S ARM Thumb
processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210
MIPS at 190 MHz.
The AT91SAM9261S is an optimized host processor for applications with an LCD display. Its
integrated LCD controller supports BW and up to 16M color, active and passive LCD displays.
The 16 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for
LCD refresh on the overall processor performance. The External Bus Interface incorporates con-
trollers for synchronous DRAM (SDRAM) and Static memories and features specific interface
circuitry for CompactFlash and NAND Flash.
The AT91SAM9261S integrates a ROM-based Boot Loader supporting code shadowing from,
for example, external DataFlash
®
into external SDRAM. The software controlled Power Manage-
ment Controller (PMC) keeps system power consumption to a minimum by selectively
enabling/disabling the processor and various peripherals and adjustment of the operating
frequency.
The AT91SAM9261S also benefits from the integration of a wide range of debug features includ-
ing JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace.
This enables the development and debug of all applications, especially those with real-time
constraints.
3
6242ES–ATARM–11-Sep-09
2. Block Diagram
Figure 2-1.
JTAGSEL
TDI
TDO
TMS
TCK
NTRST
RTCK
AT91SAM9261S Block Diagram
ARM926EJ-S Core
JTAG
Boundary Scan
ICE
Instruction Cache
16K bytes
MMU
BIU
I
D
Data Cache
16K bytes
PIO
System Controller
TST
FIQ
IRQ0-IRQ2
DRXD
DTXD
PCK0-PCK3
PLLRCA
PLLRCB
XIN
XOUT
AIC
PIO
DBGU
PDC
Fast SRAM
16K bytes
EBI
CompactFlash
NAND Flash
PLLA
PLLB
OSC
PMC
Fast ROM
32K bytes
5-layer
Matrix
PIT
Peripheral
Bridge
Peripheral
DMA
Controller
DMA
RSTC
POR
APB
PIOA
PIOB
PIOC
FIFO
USB Device
USB Host
FIFO
Transceiver
WDT
SDRAM
Controller
GPBREG
XIN32
XOUT32
SHDN
WKUP
VDDBU
GNDBU
VDDCORE
NRST
POR
OSC
RTT
SHDWC
Static
Memory
Controller
BMS
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15/A18-A21
A22/REG
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NCS2
NCS3/NANDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
SDCKE
RAS-CAS
SDWE
SDA10
NWAIT
A23-A24
A25/CFRNW
NCS4/CFCS0
NCS5/CFCS1
CFCE1
CFCE2
NCS6/NANDOE
NCS7/NANDWE
D16-D31
HDMA
HDPA
HDMB
HDPB
Transceiver
PIO
DDM
DDP
DMA
MCCK
MCCDA
MCDA0-MCDA3
FIFO
MCI
PDC
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
RXD2
TXD2
SCK2
RTS2
CTS2
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI1_NPCS10
SPI1_NPCS1
SPI1_NPCS12
SPI1_NPCS3
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
LUT
LCD Controller
LCDD0-LCDD23
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
LCDCC
TF0
TK0
TD0
RD0
RK0
RF0
TF1
TK1
TD1
RD1
RK1
RF1
TF2
TK2
TD2
RD2
RK2
RF2
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
TWD
TWCK
USART0
PDC
PDC
SSC0
USART1
PIO
PIO
SSC1
PDC
PDC
PIO
SSC2
PDC
Timer Counter
TC0
TC1
TC2
TWI
PDC
USART2
PDC
SPI0
PDC
SPI1
4
AT91SAM9261S
6242ES–ATARM–11-Sep-09
AT91SAM9261S
3. Signal Description
Table 3-1.
Signal Name
VDDIOM
VDDIOP
VDDBU
VDDPLL
VDDOSC
VDDCORE
GND
GNDPLL
GNDOSC
GNDBU
XIN
XOUT
XIN32
XOUT32
PLLRCA
PLLRCB
PCK0 - PCK3
SHDN
WKUP
TCK
RTCK
TDI
TDO
TMS
NTRST
JTAGSEL
Signal Description by Peripheral
Function
Power
EBI I/O Lines Power Supply
Peripherals I/O Lines Power Supply
Backup I/O Lines Power Supply
PLL Power Supply
Oscillator Power Supply
Core Chip Power Supply
Ground
PLL Ground
Oscillator Ground
Backup Ground
Main Oscillator Input
Main Oscillator Output
Slow Clock Oscillator Input
Slow Clock Oscillator Output
PLL Filter
PLL Filter
Programmable Clock Output
Shutdown Control
Wake-Up Input
Test Clock
Returned Test Clock
Test Data In
Test Data Out
Test Mode Select
Test Reset Signal
JTAG Selection
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Clocks, Oscillators and PLLs
Input
Output
Input
Output
Input
Input
Output
Output
Input
ICE and JTAG
Input
Output
Input
Output
Input
Input
Input
Reset/Test
Low
No pull-up resistor.
Pull-up resistor.
Pull-down resistor. Accepts
between 0V and VDDBU.
Low
Pull-up resistor
Pull-down resistor.
No pull-up resistor.
No pull-up resistor.
No pull-up resistor.
Do not tie over VDDBU.
Accepts between 0V and VDDBU.
Shutdown, Wakeup Logic
1.65 V to 1.95V and 3.0V to 3.6V
2.7V to 3.6V
1.08V to 1.32V
3.0V to 3.6V
3.0V to 3.6V
1.08V to 1.32V
Type
Active Level
Comments
NRST
TST
BMS
DRXD
DTXD
Microcontroller Reset
Test Mode Select
Boot Mode Select
Debug Receive Data
Debug Transmit Data
I/O
Input
Input
Debug Unit
Input
Output
5
6242ES–ATARM–11-Sep-09
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