NPIC6C596-Q100
Power logic 8-bit shift register; open-drain outputs
Rev. 2 — 4 July 2013
Product data sheet
1. General description
The NPIC6C596-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and open-drain outputs. Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and
an asynchronous reset MR input. A LOW on MR resets both the shift register and storage
register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in
the shift register is transferred to the storage register on a LOW-to-HIGH transition of the
STCP input. If both clocks are connected together, the shift register is always one clock
pulse ahead of the storage register. To provide additional hold time in cascaded
applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the
storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor
whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to
assume a high-impedance OFF-state. Operation of the OE input does not affect the state
of the registers.
The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS
transistors designed for use in systems that require moderate load power such as LEDs.
Integrated voltage clamps in the outputs provide protection against inductive transients
making the device suitable for power driver applications such as relays, solenoids and
other low-current or medium-voltage loads.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +125
C
Low R
DSon
Eight Power EDNMOS transistor outputs of 100 mA continuous current
250 mA current limit capability
Output clamping voltage 33 V
30 mJ avalanche energy capability
Enhanced cascading for multiple stages
All registers cleared with single input
Low power consumption
ESD protection:
HBM AEC-Q100-002 revision D exceeds 2500 V
CDM AEC-Q100-011 revision B exceeds 1000 V
Nexperia
NPIC6C596-Q100
Power logic 8-bit shift register; open-drain outputs
3. Applications
LED sign
Graphic status panel
Fault status indicator
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
NPIC6C596D-Q100
40 C
to +125
C
SO16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
NPIC6C596PW-Q100
40 C
to +125
C
NPIC6C596BQ-Q100
40 C
to +125
C
DHVQFN16 plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
5. Functional diagram
15
SHCP
10
STCP
Q0
Q1
Q2
2
3
4
5
6
11
12
13
14
9
8
10
15
7
DS
SHCP
MR
8-STAGE SHIFT REGISTER
Q7S
9
2
DS
Q3
Q4
Q5
Q6
Q7
Q7S
STCP
8-BIT STORAGE REGISTER
OE
OPEN-DRAIN OUTPUTS
Q0 Q1 Q2
3
4
5
Q3 Q4 Q5 Q6 Q7
6
11
12
13
14
aaa-002548
MR
7
OE
8
aaa-002547
Fig 1.
Logic symbol
Fig 2.
Functional diagram
NPIC6C596_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2013
2 of 21
Nexperia
NPIC6C596-Q100
Power logic 8-bit shift register; open-drain outputs
V
CC
Qn
33 V
GND
aaa-002550
GND
aaa-002551
Fig 3.
Schematic of all inputs
Fig 4.
Schematic of open-drain outputs (Qn)
STAGE 0
DS
D
FF0
CP
R
SHCP
Q
D
STAGE 1 TO 6
Q
STAGE 7
D
FF7
CP
R
Q
STAGE 7S
D
FF7
CP
R
Q
Q7S
MR
D
R
FF
Q
D
R
FF
Q
CP
CP
STCP
OE
GND
GND
aaa-002552
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Fig 5.
Logic diagram
NPIC6C596_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2013
3 of 21
Nexperia
NPIC6C596-Q100
Power logic 8-bit shift register; open-drain outputs
7
SHCP
6
5
4
3
2
1
0
5V
GND
5V
GND
5V
GND
5V
GND
5V
GND
V
OH
V
OL
aaa-002553
OE
DS
STCP
MR
Q1
Fig 6.
Timing diagram
NPIC6C596_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2013
4 of 21
Nexperia
NPIC6C596-Q100
Power logic 8-bit shift register; open-drain outputs
6. Pinning information
6.1 Pinning
NPIC6C596-Q100
terminal 1
index area
16 GND
15 SHCP
14 Q7
13 Q6
12 Q5
GND
(1)
8
9
Q7S
11 Q4
10 STCP
OE
V
CC
2
3
4
5
6
7
1
DS
V
CC
DS
Q0
Q1
Q2
Q3
MR
OE
1
2
3
4
5
6
7
8
aaa-002554
NPIC6C596-Q100
16 GND
15 SHCP
14 Q7
13 Q6
12 Q5
11 Q4
10 STCP
9
Q7S
Q0
Q1
Q2
Q3
MR
aaa-002555
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 7.
Pin configuration SO16 and TSSOP16
Fig 8.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
V
CC
DS
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
MR
OE
Q7S
STCP
SHCP
GND
Pin description
Pin
1
2
3, 4, 5, 6, 11, 12, 13, 14
7
8
9
10
15
16
Description
supply voltage
serial data input
parallel data output (open-drain)
master reset (active LOW)
output enable input (active LOW)
serial data output
storage register clock input
shift register clock input
ground (0 V)
NPIC6C596_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2013
5 of 21
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