ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
4.5 V ≤ (V
DD1
= V
DDA
) ≤ 5.5 V; V
DD2
= V
REG
= V
ISO
= 5.0 V; f
SW
= 500 kHz; all voltages are relative to their respective grounds; see the
application schematic in Figure 48. All minimum/maximum specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= V
DDA
= 5.0 V, V
DD2
= V
REG
= V
ISO
= 5.0 V.
Table 1. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Isolated Output Voltage
Feedback Voltage Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Symbol
V
ISO
V
FB
V
ISO (LINE)
V
ISO (LOAD)
V
ISO (RIP)
V
ISO (NOISE)
f
SW
192
Switch On-Resistance
Undervoltage Lockout, V
DDA
, V
DD2
Supplies
Positive Going Threshold
Negative Going Threshold
Hysteresis
DC to 2 Mbps Data Rate
3
Maximum Output Supply Current
4
Efficiency at Maximum Output Current
5
iCoupler
DATA CHANNELS
DC to 2 Mbps Data Rate
I
DD1
Supply Current, No V
ISO
Load
ADuM4470
ADuM4471
ADuM4472
ADuM4473
ADuM4474
25 Mbps Data Rate (CRIZ Grade Only)
I
DD1
Supply Current, No V
ISO
Load
ADuM4470
ADuM4471
ADuM4472
ADuM4473
ADuM4474
Available V
ISO
Supply Current
6
ADuM4470
ADuM4471
ADuM4472
ADuM4473
ADuM4474
I
DD1
Supply Current, Full V
ISO
Load
I/O Input Currents
Logic High Input Threshold
Logic Low Input Threshold
R
ON
V
UV+
V
UV−
V
UVH
I
ISO (MAX)
400
Min
4.5
1.15
Typ
5.0
1.25
1
1
50
100
1000
200
318
0.5
2.8
2.6
0.2
500
72
Max
5.5
1.37
10
2
Unit
V
V
mV/V
%
mV p-p
mV p-p
kHz
kHz
kHz
Ω
V
V
V
mA
%
f ≤ 1 MHz, V
ISO
= 5.0 V
I
ISO
= I
ISO (MAX)
, f ≤ 1 MHz
Test Conditions/Comments
I
ISO
= 0 mA,
V
ISO
= V
FB
× (R1 + R2)/R2
I
ISO
= 0 mA
I
ISO
= 50 mA,
V
DD1 1
= V
DDA 2
= 4.5 V to 5.5 V
I
ISO
= 50 mA to 200 mA
20 MHz bandwidth,
C
OUT
= 0.1 µF||47 µF, I
ISO
= 100 mA
20 MHz bandwidth,
C
OUT
= 0.1 µF||47 µF, I
ISO
= 100 mA
R
OC
= 50 kΩ
R
OC
= 270 kΩ
V
OC
= V
DD2
(open-loop)
515
I
DD1 (Q)
14
15
16
17
18
I
DD1 (D)
44
46
48
50
52
I
ISO (LOAD)
390
388
386
384
382
550
I
IA
, I
IB
, I
IC
, I
ID
V
IH
V
IL
−20
2.0
+0.01
+20
0.8
Rev. 0 | Page 4 of 36
I
ISO
= 0 mA, f ≤ 1 MHz
30
30
30
30
30
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
V
V
I
ISO
= 0 mA, C
L
= 15 pF, f = 12.5 MHz
I
ISO
= 0 mA, C
L
= 15 pF, f = 12.5 MHz
I
ISO
= 0 mA, C
L
= 15 pF, f = 12.5 MHz
I
ISO
= 0 mA, C
L
= 15 pF, f = 12.5 MHz
I
ISO
= 0 mA, C
L
= 15 pF, f = 12.5 MHz
f
SW
= 500 kHz
C
L
= 15 pF, f = 12.5 MHz
C
L
= 15 pF, f = 12.5 MHz
C
L
= 15 pF, f = 12.5 MHz
C
L
= 15 pF, f = 12.5 MHz
C
L
= 15 pF, f = 12.5 MHz
C
L
= 0 pF, f = 0 MHz, V
DD1
= V
DDA
=
5 V, I
ISO
= 400 mA
Data Sheet
Parameter
Logic High Output Voltages
ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474
Symbol
V
OAH
, V
OBH
,
V
OCH
, V
ODH
Min
V
DDA
− 0.3,
V
ISO
− 0.3
V
DDA
− 0.5,
V
ISO
− 0.5
Typ
5.0
4.8
0.0
0.0
0.1
0.4
Max
Unit
V
V
V
V
Test Conditions/Comments
I
Ox
= −20 µA, V
Ix
= V
IxH
I
Ox
= −4 mA, V
Ix
= V
IxH
I
Ox
= 20 µA, V
Ix
= V
IxH
I
Ox
= 4 mA, V
Ix
= V
IxH
Logic Low Output Voltages
V
OAL
, V
OBL
,
V
OCL
, V
ODL
AC SPECIFICATIONS
ADuM447xARIZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
|
Propagation Delay Skew
Channel-to-Channel Matching
ADuM447xCRIZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
|
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
Refresh Rate
1
2
PW
1
t
PLH
, t
PHL
PWD
t
PSK
t
PSKCD
/t
PSKOD
PW
t
PLH
, t
PHL
PWD
t
PSK
t
PSKCD
t
PSKCD
t
R
/t
F
|CM
H
|
|CM
L
|
f
r
2.5
35
35
1.0
25
30
45
5
55
1000
100
40
50
50
40
60
6
15
6
15
ns
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
kV/µs
kV/µs
Mbps
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DDA
or V
ISO
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V or V
ISO
, V
CM
= 1000 V,
transient magnitude = 800 V
25
25
V
DD1
is the power supply for the push-pull transformer.
V
DDA
is the power supply of Side 1 of the ADuM447x.
3
The contributions of supply current values for all four channels are combined at identical data rates.
4
The V
ISO
supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the V
ISO
power budget.
5
The power demands of the quiescent operation of the data channels were not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
6
This current is available for driving external loads at the V
ISO
output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.
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