74F112PC_Q datasheet, PDF - EEWORLD Datasheet

74F112PC_Q: DescriptionFlip Flops Dual J-K Flip-Flop; Categorysemiconductor logic; File Size80KB，7 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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Flip Flops Dual J-K Flip-Flop

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	ON Semiconductor
Product Category	Flip Flops
RoHS	N
Number of Circuits	2
Logic Family	74F
Logic Type	D-Type Flip-Flop
Polarity	Inverting/Non-Inverting
Input Type	Single-Ended
Output Type	Differential
Propagation Delay Time	6.5 ns
High Level Output Current	- 1 mA
Low Level Output Current	20 mA
Supply Voltage - Min	4.5 V
Supply Voltage - Max	5.5 V
Minimum Operating Temperature	0 C
Maximum Operating Temperature	+ 70 C
Mounting Style	Through Hole
Package / Case	PDIP-16
Packaging	Tube
Function	JK Type
Height	3.42 mm
Length	19.68 mm
Width	6.6 mm
Number of Channels	2
Number of Input Lines	2
Number of Output Lines	1
Operating Supply Voltage	4.5 V to 5.5 V
Reset Type	Set, Reset
Unit Weight	0.057419 oz

	74F112PC_Q
Description	Flip Flops Dual J-K Flip-Flop
Product Attribute	Attribute Value
Manufacturer	ON Semiconductor
Product Category	Flip Flops
RoHS	N
Number of Circuits	2
Logic Family	74F
Logic Type	D-Type Flip-Flop
Polarity	Inverting/Non-Inverting
Input Type	Single-Ended
Output Type	Differential
Propagation Delay Time	6.5 ns
High Level Output Current	- 1 mA
Low Level Output Current	20 mA
Supply Voltage - Min	4.5 V
Supply Voltage - Max	5.5 V
Minimum Operating Temperature	0 C
Maximum Operating Temperature	+ 70 C
Mounting Style	Through Hole
Package / Case	PDIP-16
Packaging	Tube
Function	JK Type
Height	3.42 mm
Length	19.68 mm
Width	6.6 mm
Number of Channels	2
Number of Input Lines	2
Number of Output Lines	1
Operating Supply Voltage	4.5 V to 5.5 V
Reset Type	Set, Reset
Unit Weight	0.057419 oz

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