Data Sheet
MUAA Routing CoProcessor (RCP) Family
APPLICATION BENEFITS
•
High performance MAC Address processor for
multiport switches and routers (Up to 48 10/100 or 4
Gigabit Ethernet at wire speed)
Layer 4 flow recognition for Quality of Service up to
16.7 million packets per second
ARP Cache manager/IP address caching at 12.5
million packets per second
Synchronous interfaces and programmable priority
between ports for simplicity of design
Learn, age, and auto-age functions with “virtual
queues,” keeping track of aged and learned entries
Transparent cascade of up to four 2K devices without
external logic, software setup, or performance hit
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
2K and 8K x 80-bit partitionable CAM/RAM data
field in address database
32-bit synchronous port with separate inputs and
outputs; optional 16-bit configuration
32-bit bi-directional processor port; optional 16-bit
configuration
Pipelined operation
Operations performed from the synchronous port or
processor port; all flags independently available to
both ports
9-bit internal time stamp
50 MHz clock
388-pin PBGA (8K) and 160-pin PQFP (2K)
packages.
3.3 Volt core with 3.3 Volt/5 Volt tolerant IO buffers.
IEEE 1149.1 (JTAG) compliant
•
•
•
•
•
•
•
•
•
•
Sync Port
DIN(31:0)
Processor Port DIN(31:0)
16/32 to 80-bit mux
16/32 to 80-bit mux
80-bit latch
80-bit latch
DINREADY
OP(3:0)
/DINE
80-bit 2 to 1 mux
PROCD(31:0)
/FF
PROCA(5:0)
/PCS
R/W
PROCREADY
INT
/RESET
CLK
Control
Address Data Base
-- b i t 79 -- ------- ------- b i t 0---
Flag and
Chain
Logic
/MF
CHAIN
CHAINUP
CHAINDN
/CHAINCS
/DOUTVALID
/DOUTE
/OE
Processor Port DOUT(31:0)
80-bit la tch
80-bit la tch
80 to 32/16-bit mux
80 to 32/16-bit mux
TDI
TMS
TCK
TRST
JTAG
TDO
Sync Port
DOUT(31:0)
Figure 1: Block Diagram
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are
Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of
MUSIC Semiconductors.
March 26, 2003 Rev. 5
MUAA Routing CoProcessor (RCP) Family
General Description
GENERAL DESCRIPTION
The MUSIC MUAA Routing CoProcessor (RCP) family
consists of 80-bit wide content-addressable memories
(CAMs), available in depths of 2K and 8K words. The
CAM/RAM associated data partition is programmable
from 32 bits of CAM and 48 bits of associated data, to 80
bits of CAM and 0 bits of RAM. The MUAA RCP can
perform normal routing functions such as search, insert,
and delete on single entries and can age multiple entries
simultaneously. In addition, there is a learn instruction,
particularly useful in networking applications. For
maximum flexibility all the operations may be performed
either through the processor port or through the
synchronous port. Operations may occur on both ports
simultaneously; the port with the highest priority will gain
access first if both ports require a read or write into the
CAM array simultaneously.
The synchronous interface consists of 32-bit wide input
and output ports, both of which may be configured as 16
bits. The data is multiplexed into and out of the CAM and
RAM associated data field. Where input or output data is
wider than the port, it is loaded or unloaded in multiple
cycles starting with the least significant word. Internally
the device is pipelined; once an operation is started on the
synchronous port the next operation may be loaded and the
results of the previous operation unloaded, thus
maximizing device throughput.
Multiple 2K MUAA RCPs may be chained transparently
to provide deeper memory. No software configuration is
necessary. Each MUAA RCP detects where it is in the
chain from the chaining pins on the previous device. A
register is provided to inform the host of the total available
CAM memory and the number of CAMs chained. All
operations to the chained CAM are totally transparent. No
individual device selection or addressing is required.
The MUSIC MUAA RCP has aging, auto-aging, and
learning functions. All entries have a 9-bit time stamp and
may be marked as static to prevent the aging function from
deleting them. When auto aging is enabled it may be
configured to have higher or lower priority access than the
ports.
Two internal virtual queues of learned and aged entries are
available. As entries are learned or aged out they are
tagged as such and may be read from the device through
either of the ports. This feature enables simple host
management of aged out and learned entries.
IEEE Standard. 1149.1 (JTAG) testability is implemented
providing BYPASS, SAMPLE/PRELOAD, EXTEST,
CLAMP, and HIGH-Z functions.
2
Rev. 5
Pin Descriptions
MUAA Routing CoProcessor (RCP) Family
PIN DESCRIPTIONS
Note:
Signal names that start with a slash (“/”) are active LOW. All signals are 3.3 Volt CMOS level. All input and bi-directional pins
are 5-Volt tolerant, except for CLK. Never leave inputs floating except where indicated. The CAM architecture draws large currents
during search operations, mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section
for more information.
See Table 1 for the 388-pin balls and the Packages section for the chip illustrations.
VCC
DOUT0
GND
DIN31
DIN30
DIN29
DIN28
DIN27
GND
DIN26
DIN25
DIN24
DIN23
DIN22
DIN21
VCC
DIN20
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
GND
DIN13
DIN12
DIN11
DIN10
DIN9
DIN8
DIN7
VCC
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
GND
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
GN D
DOUT1
DOUT2
DOUT3
DOUT4
VCC
DOUT5
DOUT6
DOUT7
GN D
DOUT8
DOUT9
DOUT10
DOUT11
VCC
DOUT12
DOUT13
DOUT14
DOUT15
GN D
DOUT16
DOUT17
DOUT18
DOUT19
VCC
DOUT20
DOUT21
DOUT22
DOUT23
GN D
DOUT24
DOUT25
DOUT26
DOUT27
VCC
DOUT28
DOUT29
DOUT30
DOUT31
GN D
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
160-Pin
PQFP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VCC
CH A IND N
CH A INUP
GN D
CH A IN3
CH A IN2
CH A IN1
CH A IN0
GN D
CH AI NCS
PROCD31
PROCD30
PROCD29
PROCD28
PROCD27
PROCD26
PROCD25
PROCD24
VCC
PROCD23
PROCD22
PROCD21
PROCD20
PROCD19
PROCD18
GN D
PROCD17
PROCD16
PROCD15
PROCD14
PROCD13
PROCD12
VCC
PROCD11
PROCD10
PROCD9
PROCD8
PROCD7
PROCD6
GN D
DIN[31:0] (Input)
DIN[31:0] are synchronous port data input pins. Data is
loaded into the MUAA RCP right aligned, least significant
word first.
/DINE (Input)
DIN is sampled by the rising edge of CLK when /DINE is
asserted. Refer to Table 1 for slave connections.
OP[3:0] (Input)
OP[3:0] is a synchronous port operation to be performed
on the data applied to the DIN pins. OP is sampled by the
rising edge of CLK when /DINE is asserted. When loading
the CAM/RAM words to DIN, OP is set to LOAD except
for the last word. OP for the last word is set to the desired
operation.
Rev. 5
VCC
CLK
GND
/MF
/FF
/DOUTVALID
DINREADY
INT
PROCREADY
TDO
GND
TDI
TMS
TCK
/TRST
/OE
/DOUTE
/DINE
OP0
OP1
OP2
OP3
VCC
PROCA0
PROCA1
PROCA2
PROCA3
PROCA4
PROCA5
R/W
/PCS
/RESET
GND
PROCD0
PROCD1
PROCD2
PROCD3
PROCD4
PROCD5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Figure 2: 160-Pin PQFP (Top View)
DINREADY (Output)
When DINREADY is HIGH, the synchronous port
accepted the current operation. This is affected by the
priority set for the DIN port and the processor port. Note,
DINREADY may be LOW for up to 800 CLK periods
after /RESET is taken HIGH. The JTAG interface is able
to set DINREADY to HIGH-Z. Active HIGH.
DOUT[31:0] (3-State Output)
DOUT[31:0] is the synchronous port data output. Data is
read out right aligned, least significant word first. The
address index (bits 25–0), SWEX flag (bit 26), PWEX flag
(bit 27), LQUEUE flag (bit 28), AQUEUE flag (bit 29),
Sync Port Match flag (bit 30), and Full flag (bit 31) may
also be read from this port before or after operation data
depending on configuration.
3
MUAA Routing CoProcessor (RCP) Family
Pin Descriptions
/DOUTVALID (Output)
/DOUTVALID indicates when new data is available at the
synchronous output port. /DOUTVALID is active LOW
for one CLK cycle. /DOUTVALID may be configured to
become active on the same clock as new DOUT becomes
valid or the CLK before. The JTAG interface is able to set
/DOUTVALID to HIGH-Z.
/OE (Input)
/OE is the DOUT High Impedance control.
/DOUTE (Input)
/DOUTE is the DOUT enable control. When the DOUT
data word is configured to be wider than the output port
then this strobe enables the next word(s) of the DOUT data
onto the DOUT pins.
PROCD[31:0] (Bi-directional)
The bi-directional Processor data port provides the
processor interface to the device. On write cycles all
devices respond in parallel. On read cycles the appropriate
device responds without additional intervention from the
processor.
PROCA[5:0] (Input)
Processor port address bus. Selects which device register
is accessed. Bit 0 is only used when the port is set to 16-bit
mode, otherwise it should be held at a valid logic level.
R/W (Input)
R/W is the processor port read/write control pin. This pin
is HIGH for reads, LOW for writes.
/PCS (Input)
/PCS is the processor port chip select pin. When LOW this
pin indicates a cycle to the processor port. On write cycles
data must be set up to the rising edge of /PCS. On read
cycles /PCS controls the output enable of the PROCD bus.
Note that /PCS may be asynchronous to CLK. Refer to
Table 1 for slave connections.
PROCREADY (Output)
When PROCREADY is HIGH, indicates the processor
read data is available or the processor write data is
accepted. Priority may be set between the DIN port and
the processor port. Note PROCREADY may be LOW for
up to 800 CLK periods after /RESET is taken HIGH. The
JTAG interface is able to set PROCREADY to HIGH-Z.
INT (Output)
INT interrupt. Indicates the aged or learned queue has at
least one entry or a write exception occurred. The service
routine should either check the AQUEUE, LQUEUE, and
WEX registers, or bits 26–29 of the Address Index
register, to determine the cause. The interrupt is cleared
after the appropriate flag register has been read and will
not be reasserted until either the queue(s) are emptied and
4
then get at least one entry again, or another write
exception occurs. The JTAG interface is able to set INT to
HIGH-Z.
/RESET (Input)
The /RESET input is used to reset the MUAA RCP.
/RESET must be asserted for at least 3 CLK periods.
CLK (Input)
The rising edge of CLK input is the device clock.
/FF (Full Flag, Output)
/FF is active when the device (or chain of devices) is full.
/FF becomes inactive when any one device has two open
entries. The JTAG interface is able to set /FF to HIGH-Z.
CHAIN[3:0 (Input)
When two or more devices are chained they communicate
among themselves using the CHAIN[3:0] signals. See
Chaining section. Internally Pulled-up. Refer to Table 1
for slave connections.
CHAINUP (Output)
When two or more devices are chained they communicate
among themselves using the CHAINUP signals. See
Chaining section. The JTAG interface is able to set
CHAINUP to HIGH-Z. Refer to Table 1 for slave
connections.
CHAINDN (Output)
When two or more devices are chained they communicate
among themselves using the CHAINDN signals. See
Chaining section. The JTAG interface is able to set
CHAINDOWN to HIGH-Z. Refer to Table 1 for slave
connections.
CHAINCS (Bi-directional)
When two or more devices are chained they communicate
among themselves using the CHAINCS signals. See
Chaining section. Internally pulled up. Refer to Table 1 for
slave connections.
/MF (Match Flag, Output)
The /MF output indicates whether a match was found. The
JTAG interface is able to set /MF to HIGH-Z.
/TRST (JTAG Reset, Input)
The /TRST is the Test Reset pin. Internally pulled up with
25K minimum. Must be tied to /RESET or tied LOW
when not in use.
/TCLK (JTAG Test Clock, Input)
The /TCLK input is the Test Clock input. Must be tied at a
valid logic level when not in use.
TMS (JTAG Test Mode Select, Input)
The TMS input is the Test Mode Select input. Internally
pulled up with 25K minimum.
Rev. 5
Pin Descriptions
MUAA Routing CoProcessor (RCP) Family
TDI (JTAG Test Data Input, Input)
The TDI input is the Test Data input. Internally pulled up
with 25K minimum. Refer to Table 1 for slave
connections.
TDO (JTAG Test Data Output, Output)
The TDO output is the Test Data output. Refer to Table 1
for slave connections.
VCC, GND
These pins are the power supply connection to the MUAA
RCP. VCC must meet the voltage supply requirements in
the Operating Conditions section relative to the GND pins,
which are at 0 Volts (system reference potential), for
correct operation of the device. All the ground and power
pins must be connected to their respective planes with
adequate bulk and high frequency bypassing capacitors in
close proximity to the device.
Ball Descriptions
Table 1: Ball Descriptions
Functional
Group
Synchronous
Input Port
Ball Name(s)
DIN[31:0]
Function
Synchronous port data input.
Type
Input
5V tol
PBGA Ball(s)
b0:AA26, b1:AA25, b2:Y26,
b3:Y25, b4:W26, b5:W25,
b6:V26, b7:V25, b8:U26,
b9:U25, b10:T26, b11:T25,
b12:R26, b13:R25, b14:P26,
b15:P25, b16:N26, b17:N25,
b18:M26, b19:M25, b20:L26,
b21:L25, b22:K26, b23:K25,
b24:J26, b25:J25, b26:H26,
b27:H25, b28:G26, b29:G25,
b30:F26, b31:F25
T1
T2
R2
P2
b0:U1, b1:U2, b2:U3, b3:T3
H1
/DINE
/DINE-S1
/DINE-S2
/DINE-S3
OP[3:0]
DINREADY
CLK
Synchronous
Output Port
DOUT[31:0]
When asserted, DIN is sampled by the rising edge of
CLK. Connect to T2, R2, and P2.
Slave 1. Connect to T1, /DINE.
Slave 2. Connect to T1, /DINE.
Slave 3. Connect to T1, /DINE.
Synchronous port operation performed on data
applied to DIN pins.
When HIGH, indicates the synchronous port
accepted the current operation.
Rising edge is the device clock.
Synchronous port data output.
Input
5V tol
Input
5V tol
Input
5V tol
Input
5V tol
Input
5V tol
Output
Input
D1
3.3V only
Output
b0:A21, b1:B21, b2:A20,
b3:B20, b4:A19, b5:B19,
b6:A18, b7:B18, b8:A17,
b9:B17, b10:A16, b11:B16,
b12:A15, b13:B15, b14:A14,
b15:B14, b16:A13, b17:B13,
b18:A12, b19:B12, b20:A11,
b21:B11, b22:A10, b23:B10,
b24:A9, b25:B9, b26:A8,
b27:B8, b28:A7, b29:B7,
b30:A6, b31:B6
G1
P1
R1
E1
/DOUTVALID
/OE
/DOUTE
/MF
Indicates when new data is available at the
synchronous output port.
DOUT high impedance control.
DOUT enable control.
Match flag. Indicates if a match was found.
Output
Input
5V tol
Input
5V tol
Output
Rev. 5
5
京公网安备 11010802033920号
EEWORLD
