IDT71V65703S80BG8 datasheet, PDF

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IDT71V65703S80BG8: DescriptionZBT SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119; Categorystorage; File Size491KB，26 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71V65703S80BG8 Overview

ZBT SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119

IDT71V65703S80BG8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	8 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	95 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	2.36 mm
Maximum standby current	0.04 A
Minimum standby current	3.14 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

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256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter

Flow-Through Outputs

Features

256K x 36, 512K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V (±5%) I/O Supply (V

DDQ

)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

IDT71V65703

IDT71V65903

Description

The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.

They are designed to eliminate dead bus cycles when turning the bus

around between reads and writes, or writes and reads. Thus they have

been given the name ZBT

, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock

cycle, and on the next clock cycle the associated data cycle occurs, be it

read or write.

The IDT71V65703/5903 contain address, data-in and control signal

registers. The outputs are flow-through (no output data register). Output

enable is the only asynchronous signal and can be used to disable the

outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903

tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen

CEN

is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE

, CE

) that allow the

user to deselect the device when desired. If any one of these three is not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state one cycle after the chip is deselected or a write

is initiated.

The IDT71V65703/5903 have an on-chip burst counter. In the burst

mode, the IDT71V65703/5903 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the

LBO

input pin. The

LBO

pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH).

The IDT71V65703/5903 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC Standard 14mm x 20mm 100-

pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165

fine pitch ball grid array (fBGA).

Pin Description Summary

-A

, CE

R/W

CEN

CLK

ADV/LD

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance Burst Address/Load New Address

Linear/Interleaved Burst Order

Sleep Mode

Data Input/Output

Core Power, I/O Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Asynchronous

Synchronous

Static

5298 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

DECEMBER 2002

DSC-5298/03

IDT71V65703S80BG8 Related Products

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Description	ZBT SRAM, 256KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119	ZBT SRAM, 256KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119	ZBT SRAM, 512KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119	ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119	ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100	ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-026AA, BGA-119
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	BGA	BGA	BGA	QFP	BGA	QFP	BGA
package instruction	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100	BGA, BGA119,7X17,50	14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100	14 X 22 MM, PLASTIC, MS-026AA, BGA-119
Contacts	119	119	119	100	119	100	119
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	8 ns	8.5 ns	8 ns	7.5 ns	7.5 ns	7.5 ns	7.5 ns
Other features	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	95 MHz	90 MHz	95 MHz	100 MHz	100 MHz	100 MHz	100 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PQFP-G100	R-PBGA-B119	R-PQFP-G100	R-PBGA-B119
JESD-609 code	e0	e0	e0	e0	e0	e0	e0
length	22 mm	22 mm	22 mm	20 mm	22 mm	20 mm	22 mm
memory density	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit
Memory IC Type	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM
memory width	36	36	18	18	36	18	18
Humidity sensitivity level	3	3	3	3	3	3	3
Number of functions	1	1	1	1	1	1	1
Number of terminals	119	119	119	100	119	100	119
word count	262144 words	262144 words	524288 words	524288 words	262144 words	524288 words	524288 words
character code	256000	256000	512000	512000	256000	512000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	85 °C	70 °C	70 °C	70 °C
organize	256KX36	256KX36	512KX18	512KX18	256KX36	512KX18	512KX18
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	LQFP	BGA	LQFP	BGA
Encapsulate equivalent code	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50	QFP100,.63X.87	BGA119,7X17,50	QFP100,.63X.87	BGA119,7X17,50
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	FLATPACK, LOW PROFILE	GRID ARRAY	FLATPACK, LOW PROFILE	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	225	225	225	240	225	240	NOT SPECIFIED
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.36 mm	2.36 mm	2.36 mm	1.6 mm	2.36 mm	1.6 mm	2.36 mm
Maximum standby current	0.04 A	0.04 A	0.04 A	0.06 A	0.04 A	0.04 A	0.04 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.25 mA	0.225 mA	0.25 mA	0.295 mA	0.275 mA	0.275 mA	0.275 mA
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn63Pb37)
Terminal form	BALL	BALL	BALL	GULL WING	BALL	GULL WING	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	0.65 mm	1.27 mm	0.65 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	QUAD	BOTTOM	QUAD	BOTTOM
Maximum time at peak reflow temperature	20	20	20	20	20	20	NOT SPECIFIED
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Is it lead-free?	Contains lead	Contains lead	Contains lead	-	Contains lead	-	-
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Base Number Matches	1	1	1	1	1	-	-

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