December 2006
HYS72T512341HHP–[3.7/5]–B
HYS72T512341HJP–[3.7/5]–B
HYS72T512341HKP–[3.7/5]–B
240-Pin Registered DDR2 SDRAM Modules
DDR2 SDRAM
RoHs Compliant Products
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B
Registered DDR2 SDRAM Modules
HYS72T512341HHP–[3.7/5]–B, HYS72T512341HJP–[3.7/5]–B, HYS72T512341HKP–[3.7/5]–B
Revision History: 2006-12, Rev. 1.0
Page
All
All
All
Chapter 4
Subjects (major changes since last revision)
Qimonda update
Adapted internet edition
Added HYS672T512341HJP-[3.7/5]-B and HYS72T512341HKP-[3.7/5]-B modules
SPD codes updated
Previous Revision: 2006-07, Rev. 0.5
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
11032006-VX0M-M6IH
2
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B
Registered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 1.8 V 240-Pin Registered DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
Serial Presence Detect with E
2
PROM
RDIMM Dimensions (nominal): 18,30 mm high, 133.35
mm wide
All speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications.
RoHS compliant products
1)
• 240-pin PC2–4200 and PC2–3200 DDR2 SDRAM
memory modules.
• Four rank 512M
×72
module organization, and 512M
×4
chip organization
• Registered DIMM Parity bit for address and control bus
• 4 GB module built with 512 Mbit DDR2 SDRAMs in SG-
A4FBGA-60 and PG-A4FBGA-60 chipsize packages.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• Programmable CAS Latencies (3, 4, 5),
Burst Length (4 & 8) and Burst Type
• Auto Refresh (CBR) and Self Refresh
TABLE 1
Performance Table
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
200
200
200
15
15
40
55
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
266
266
200
15
15
45
60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.0, 2006-12
11032006-VX0M-M6IH
3
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B
Registered DDR2 SDRAM Modules
1.2
Description
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E
2
PROM device using the 2-ball I
2
C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
The Qimonda HYS72T512341H[H/J/K]P–[3.7/5]–B module
family are Very Low Profile Registered DIMM (with parity)
modules with 18,3 mm height based on DDR2 technology.
DIMMs are available as ECC modules in 512M
×72
(4 GB)
organization and density, intended for mounting into 240-Ball
connector sockets.
The memory array is designed with 512-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2–4200
HYS72T512341HHP–3.7–B
HYS72T512341HJP–3.7–B
HYS72T512341HKP–3.7–B
PC2–3200
HYS72T512341HHP–5–B
HYS72T512341HJP–5–B
HYS72T512341HKP–5–B
4 GB 4R×4 PC2–3200P–333–12–ZZ
4 GB 4R×4 PC2–3200P–333–12–ZZ
4 GB 4R×4 PC2–3200P–333–12–ZZ
4 Rank ECC
4 Rank ECC
4 Rank ECC
4 GB (×4)
4 GB (×4)
4 GB (×4)
4 GB 4R×4 PC2–4200P–444–12–ZZ
4 GB 4R×4 PC2–4200P–444–12–ZZ
4 GB 4R×4 PC2–4200P–444–12–ZZ
4 Rank ECC
4 Rank ECC
4 Rank ECC
4 GB (×4)
4 GB (×4)
4 GB (×4)
Compliance Code
2)
Description
SDRAM Technology
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T512341HJP-3.7-B, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see
Chapter 6
of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–12”, where 4200P
means Registered DIMM modules (Parity bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2.
TABLE 3
Address Format
DIMM Density Module Organization
4 GB
512M
×72
Memory Ranks
4
ECC/
Non-ECC
ECC
# of SDRAMs
18
×4
# of row/bank/column bits
14/2/11
TABLE 4
Components on Modules
Product Type
HYS72T512341HHP
HYS72T512341HJP
HYS72T512341HKP
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
DRAM Components
HYB18T2G401BHF
DRAM Density
512 Mbit
DRAM Organisation
512M
×4
Note
1)
Rev. 1.0, 2006-12
11032006-VX0M-M6IH
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B
Registered DDR2 SDRAM Modules
2
2.1
Pin Configuration
Pin Configuration
and
Table 7
respectively. The pin numbering is depicted in
Figure 1.
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in
Table 5
(240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in
Table 6
TABLE 5
Pin Configuration of RDIMM
Pin No.
Clock Signals
185
186
52
171
CK0
CK0
CKE0
CKE1
NC
Control Signals
193
76
220
221
192
74
73
18
Address Signals
71
190
54
BA0
BA1
BA2
NC
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Not Connected
Less than 1Gb DDR2 SDRAMS
Bank Address Bus 1:0
S0
S1
S2
S3
RAS
CAS
WE
RESET
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
CMOS
Register Reset
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select Rank 3:0
I
I
I
I
NC
SSTL
SSTL
SSTL
SSTL
—
Clock Enables 1:0
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
Clock Signal CK0, Complementary Clock Signal CK0
Name
Pin
Type
Buffer
Type
Function
Rev. 1.0, 2006-12
11032006-VX0M-M6IH
5
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