HV66
32-Channel LCD Driver
with Separate Backplane Output
Ordering Information
Package Options
Device
HV66
44 Lead Quad
Plastic Gullwing
HV66PG
44 J-Lead Quad
Plastic Chip Carrier
HV66PJ
Die
in waffle pack
HV66X
Features
Processed with HVCMOS
¨
technology
32 push-pull CMOS output up to 60V
Low power level shifting
Source/sink current minimum 1mA
Shift register speed 5MHz
Latched data outputs
Bidirectional shift register (DIR)
Backplane output
General Description
The HV66 is a low-voltage serial to high-voltage parallel converter
with push-pull outputs. This device has been designed for use as
a driver circuit for LCD displays. It can also be used in any
application requiring multiple output high-voltage current sourc-
ing and sinking capabilities. The inputs are fully CMOS compat-
ible.
The device consists of a 32-bit shift register, 32 latches, and
control logic to perform blanking and polarity control of the
outputs. HV
OUT1
is connected to the first stage of the shift register.
Data is shifted through the shift register on the logic rising
transition of the clock. A DIR pin causes data shifting clockwise
when grounded and counterclockwise when connected to V
DD
. A
data output buffer is provided for cascading devices. This output
reflects the current status of the last bit of the shift register.
Operation of the shift register is not affected by the LE (latch
enable), BL (blank) or the POL (polarity) inputs. Transfer of data
from the shift register to the latch occurs when the LE (latch
enable) input is high. The data in the latch is stored after LE
transitions from high to low.
Absolute Maximum Ratings
1
Supply voltage, V
DD2
Output voltage, V
PP2
Logic input levels
2
Ground current
3
Continuous total power dissipation
4
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
-0.5V to +7.0V
-0.5V to +70V
-0.5V to V
DD
+ 0.5V
1.5A
1200mW
-40°C to +85°C
-65°C to +125°C
260°C
Notes:
1. Device will survive (but operation may not be specified or guaranteed) at
these extremes.
2. All voltages are referenced to V
SS
.
3. Duty cycle is limited by the total power dissipated in the package.
4. For operation above 25°C ambient derate linearly to 85°C at 20mW/°C.
09/30/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1
HV66
Electrical Characteristics
(over recommended operating conditions unless noted)
DC Characteristics
(V
DD
= 5V, V
PP
= 60V, V
SS
= GND)
Symbol
I
DD
I
PPQ
I
DDQ
V
OH
V
OL
I
IH
I
IL
V
OLBP
V
OHBP
Parameter
V
DD
supply current
High voltage supply current
Min
Max
15
0.5
0.5
Quiescent V
DD
supply current
High-level output
Q
Data out
Low-level output
Q
Data out
High-level logic input current
Low-level logic input current
Low-level output voltage, backplane
High-level output voltage, backplane
29
50
4.6
8
0.4
1
-1
3
0.5
Units
mA
mA
mA
mA
V
V
V
V
µA
µA
V
V
Conditions
V
DD
= V
DD
max
f
CLK
= 5MHz
Outputs high
Outputs low
All V
IN
= V
SS
or V
DD
I
O
= -5mA, V
PP
= 60V
I
O
= -100µA
I
O
= 5mA, V
PP
= 60V
I
O
= 100µA
V
IH
= V
DD
V
IL
= 0V
I
O
= 10mA
I
O
= -10mA
AC Characteristics
(V
DD
= 5V, V
PP
= 60V, T
C
= 25°C), logic input rises/fall time = 10ns.
Symbol
f
CLK
t
W
t
SU
t
H
t
ON
, t
OFF
t
ON
, t
OFF
t
DHL
t
DLH
t
DLE
t
WLE
t
SLE
t
BR
, t
BF
t
BR
- t
BF
Parameter
Clock frequency
Clock width high or low
Data set-up time before clock rises
Data hold time after clock rises
Time from latch enable or POL to HV
OUT
Time from POL to BP output
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
Width of LE pulse
LE set-up time before clock rises
BP
OUT
rise/fall time
BP
OUT
rise and fall difference
50
100
50
10
1000
100
100
25
50
500
500
200
200
Min
Max
5
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
C
L
= 350nF
C
L
= 350nF
C
L
= 20pF
C
L
= 20pF
C
L
= 10pF
C
L
= 10pF
Conditions
Recommended Operating Conditions
Symbol
V
DD
V
PP
V
IH
V
IL
f
CLK
T
A
I
OD
Logic supply voltage
Output voltage*
High-level input voltage
Low-level input voltage
Clock frequency
Operating free-air temperature
Allowable current through output diodes
Parameter
Min
4.5
0
2.4
0
0
-40
Max
5.5
60
V
DD
0.8
5
+85
200
Units
V
V
V
V
MHz
°C
mA
Notes:
*Output will not switch below 12V.
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
Power-down sequence should be the reverse of the above.
The V
PP
should not drop below V
DD
during operation.
3.
4.
Set all inputs (Data, CLK, Enable, etc.) to a known state.
Apply V
PP
.
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