Ordering number : EN5875
CMOS IC
LC72708E
FM Multiplex Broadcast Reception IC
for Mobile VICS Systems
Overview
The LC72708E is a data demodulation IC for receiving
FM multiplex broadcasts for mobile receivers in the
DARC format. The LC72708E also includes a built-in
decoder circuit that performs VICS data processing. This
allows this IC to implement compact high-functionality
VICS reception systems. Note that a contract with VICS
Center is required to evaluate samples of this IC or to
mass produce products that support the VICS system.
Package Dimensions
unit: mm
3148-QIP44MA
[LC72708E]
Functions
•
•
•
•
•
•
•
•
•
•
•
•
•
SCF-based adjustment-free 76-kHz bandpass filter
VICS decoder circuit
MSK delay detection circuit based on a 1T delay
Error correction function based on a 2T delay (in the
MSK detector stage)
Digital PLL based clock regeneration circuit
Shift-register type 1T and 2T delay circuits
Block and frame synchronization detection circuit
Function for setting the number of allowable BIC errors,
the number of synchronization protection.
Error correction using (272, 190) codes
Layer 4 CRC code checking circuit
On-chip frame memory and memory control circuit for
vertical correction
7.2-MHz crystal oscillator circuit
Two power saving functions (Standby and EC stop)
SANYO: QIP44MA
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
71598RM (OT) No. 5875-1/15
LC72708E
Specifications
Absolute Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Parameter
Maximum supply voltage
Input voltage
Symbol
V
DD
max
V
IN
1
V
IN
2
V
OUT
1
V
OUT
2
I
OUT
Pd max
Topr
Tstg
Ta
≤
85°C
CE, CL, DI, RST, STNBY
Pins other than V
IN
1
DO
Pins other than V
OUT
1
BLOCK, FLOCK, BCK, FCK, DO
Conditions
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to V
DD
+0.3
–0.3 to +7.0
–0.3 to V
DD
+0.3
0 to 4.0
250
–40 to +85
–55 to +125
Unit
V
V
V
V
V
mA
mW
°C
°C
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Allowable Operating Ranges
at Ta = –40 to +80°C, V
SS
= 0 V
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
Oscillator frequency
Input sensitivity
Input amplitude
[Serial I/O*]
Clock low-level time
Clock high-level time
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
Data latch change time
Data output time
Layer 4 CRC change time
Note
*:
See the serial data timing chart.
t
CL
t
CH
t
SU
t
HD
t
EL
t
ES
t
EH
t
LC
t
DD0
t
CRC
CL
CL
CL, DI
CL, DI
CL, CE
CL, CE
CL, CE
CE
DO, CL
CRC4, CL
277
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
555
0.7
µs
µs
µs
µs
µs
µs
µs
µs
ns
µs
Symbol
V
DD
V
IH
V
IL
F
OSC
V
XI
V
MPX
CL, CE, DI, RST, STNBY
CL, CE, DI, RST, STNBY
This IC operates at frequencies within a
±250 ppm precision
With a capacitance-coupled sine wave input
to X
IN
MPXIN, 100% modulation composite
400
150
Conditions
Ratings
min
4.5
0.7 V
DD
V
SS
7.2
1500
500
typ
max
5.5
5.5
0.3 V
DD
Unit
V
V
V
MHz
mVrms
mVrms
Electrical Characteristics
at V
DD
= 4.5 to 5.5 V, in the allowable operating ranges
Parameter
Output high-level voltage
Output low-level voltage
Input high-level current
Input low-level current
Input resistance
Reference supply voltage output
Bandpass filter center frequency
–3 dB bandwidth
In-band delay time difference
Gain
Symbol
V
OH
1
V
OL
1
V
OL
2
I
IH
1
I
IH
2
I
IL
R
MPX
V
REF
F
C
F
BW
D
GD
Gain
ATT1
ATT2
Stop band attenuation
ATT3
ATT4
Conditions
I
O
= 2 mA, BCK, FCK, BLOCK, FLOCK,
CRC4, INT, CLK16, DATA, IC1, IC2
I
O
= 2 mA, applies to the same pins as V
OH
1
I
O
= 2 mA, DO
V
IN
= 5.5 V, CE, CL, DI, RST, STNBY
V
IN
= V
DD
D, input pins other than I
IH
1
V
IN
= V
SS
D, CL, CE, DI, RST, STNBY,
TP0 to TP8, TPC1 to 2, TOSEL1 to 2, TEST
MPXIN-Vssa, f = 0 to 100 kHz
V
REF
, Vdda = 5 V
FLOOUT
FLOUT
FLOUT
MPXIN-FLOUT, f = 76 kHz
FLOUT, f = 50 kHz
FLOUT, f = 100 kHz
FLOUT, f = 30 kHz
FLOUT, f = 150 kHz
25
15
50
50
20
50
2.5
76.0
19.0
±5
Ratings
min
V
DD
– 0.4
0.4
0.4
1.0
1.0
–1.0
typ
max
Unit
V
V
V
µA
µA
µA
kΩ
V
kHz
kHz
µs
dB
dB
dB
dB
dB
Continued on next page.
No. 5875-2/15
LC72708E
Continued from preceding page.
Parameter
Output off leakage current
Hysteresis voltage
Internal feedback resistor
Current drain
Symbol
I
OFF
V
HIS
R
f
I
DD
V
O
= V
DD
D, DO
CL, CE, DI, RST, STNBY
X
IN
, X
OUT
0.1 V
DD
1.0
18
25
Conditions
Ratings
min
typ
max
5
Unit
µA
V
MΩ
mA
Block Diagram
1T delay
Clock
regeneration
2T delay
Synchronization
regeneration
Timing
control
Error
correction
Layer 2
CRC
MSK
correction
PN
decoding
Data
Antialiasing
filter
VICS processing
circuit
Memory array
Layer 4 CRC
Output control
(CPU interface)
Address
Pin Assignment
No. 5875-3/15
LC72708E
Pin Descriptions
Pin No.
28
29
30
33
32
40
9
12
13
14
15
16
17
18
19
41
42
5
6
7
8
20
21
22
25
26
27
3
4
Pin Name
CL
CE
DI
RST
STNBY
TEST
TP0
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TPC1
TPC2
TOSEL1
TOSEL2
CLK16
DATA
FCK
BCK
FLOCK
BLOCK
CRC4
INT
IC1
IC2
Clock regeneration monitor
Demodulated data monitor
Frame start signal output
Block start signal output
Outputs a high level during frame synchronization.
Outputs a high level during block synchronization.
Layer 4 CRCC check result output
External CPU interrupt signal
Internal connections. These pins must be left open.
Output
Must be connected to either V
DD
or V
SS
.
Input
CCB serial interface
Function
Clock input
Data control input
Data input
System reset input (active low)
Standby mode (active high)
Test (Must be connected to ground during normal operation.)
Input
I/O
Circuit type
31
DO
Data output used by the CCB serial interface
Output
44
1
XIN
XOUT
System clock generation crystal oscillator element connections
Input
Output
36
MPXIN
Baseband (multiplex) signal input
Input
38
FLOUT
Subcarrier output (76-kHz filter output)
Output
39
CIN
Subcarrier input (comparator input)
Input
Continued on next page.
No. 5875-4/15
LC72708E
Continued from preceding page.
Pin No.
Pin Name
Function
I/O
Circuit type
35
V
REF
Reference voltage output (Vdda/2)
Output
37
34
2, 10, 24
11,23, 43
V
DD
A
V
SS
A
V
DD
D
V
SS
D
Analog system power supply
Analog system ground
Digital system power supply (4.5 to 5.5 V)
Digital system ground
—
—
—
—
Note: A capacitor of at least 2000 pF must be inserted between V
DD
D and V
SS
D when using this IC.
Data I/O Techniques
• CCB Technique
Sanyo audio ICs input and output data using the Sanyo CCB (computer control bus) standard, which is a serial bus
format. This IC uses an 8-bit address CCB and uses the following addresses.
I/O mode
Input
Output
Input
Address
B0
0
1
0
B1
1
1
0
B2
0
0
1
B3
1
1
1
A0
1
1
1
A1
1
1
1
A2
1
1
1
A3
1
1
1
16-bit control data input
Data output for the input clock (CL)
Data input (in 8-bit units) for the layer 4 CRC check circuit
Function
• Data Input Timing
Internal data latching
• Data Output Timing
Note:The DO pin is normally left open.
Since the DO pin is an n-channel open drain pin, the time required for the data to change from the low level to the high level depends on the value of
the pull-up resistor.
No. 5875-5/15
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