7215J60V3ME3 datasheet, PDF - EEWORLD Datasheet

7215J60V3ME3: DescriptionTOGGLE SWITCH, DPDT, MOMENTARY, 5A, 28VDC, THROUGH HOLE-STRAIGHT; Categoryswitch Toggle switch; File Size3MB，22 Pages; ManufacturerC&K

Download Datasheet Parametric View All

7215J60V3ME3 Overview

TOGGLE SWITCH, DPDT, MOMENTARY, 5A, 28VDC, THROUGH HOLE-STRAIGHT

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	C&K
Reach Compliance Code	not_compliant
ECCN code	EAR99
Actuator type	LEVER
body width	8.13 mm
body height	11.68 mm
Body length or diameter	15.75 mm
Contact (AC) maximum rated R load	5A@120VAC
Maximum contact current (AC)	5 A
Maximum contact current (DC)	5 A
Contact (DC) maximum rated R load	5A@28VDC
Maximum contact voltage (AC)	120 V
Maximum contact voltage (DC)	28 V
Electrical life	40000 Cycle(s)
JESD-609 code	e0
Manufacturer's serial number	7000
Installation features	THROUGH HOLE-STRAIGHT
Maximum operating temperature	85 °C
Minimum operating temperature	-30 °C
seal	EPOXY TERMINAL SEALED
surface mount	NO
Switch action	MOMENTARY
switch function	DPDT
Switch type	TOGGLE SWITCH
Terminal surface	Tin/Lead (Sn/Pb) - with Nickel (Ni) barrier
Termination type	SOLDER
Base Number Matches	1

【Xianji HPM6750 Review】Interim (Final) Summary: Time flies. It has been two months since I received the board. A few days ago, the administrator said that the progress will be finished on June 30. I was surprised that it was so fast. It felt like t...; littleshrimp Domestic Chip Exchange

Shortlist | 2020-2021 ON Semiconductor and Avnet IoT Creative Design Competition: [Competition Details] 2020-2021 ON Semiconductor and Avnet IoT Creative Design CompetitionThank you very much for your support of this competition!The finalists were selected by ON Semiconductor, Avne...; EEWORLD社区 onsemi and Avnet IoT Innovation Design Competition

FPGA_100 Days Journey_Key Debounce.pdf: FPGA_100 Days Journey_Key Debounce.pdf...; zxopenljx EE_FPGA Learning Park

CSM Code Security Module FAQ: Naming convention -- CSM: Code Security Module Code Security Module -- ECSL: Emulation Code Security Logic Emulation Code Security LogicFrequently asked questions Q: What happens when the CSM automati...; Jacktang Microcontroller MCU

FPGA implementation of DVI output image selection interception.pdf: FPGA implementation of DVI output image selection interception.pdf...; zxopenljx EE_FPGA Learning Park

ASIC Design-FPGA Prototype Verification: ASIC Design-FPGA Prototype Verification...; 雷北城 FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components