CMOS PARALLEL-TO-SERIAL FIFO
256 x 16, 512 x 16, 1,024 x 16
Integrated Device Technology, Inc.
IDT72105
IDT72115
IDT72125
FEATURES:
•
•
•
•
•
•
•
•
•
25ns parallel port access time, 35ns cycle time
45MHz serial output shift rate
Wide x16 organization offering easy expansion
Low power consumption (50mA typical)
Least/Most Significant Bit first read selected by asserting
the FL/DIR pin
Four memory status flags: Empty, Full, Half-Full, and
Almost-Empty/Almost-Full
Dual-Port zero fall-through architecture
Available in 28-pin 300 mil plastic DIP and 28-pin SOIC
Industrial temperature range (–40°C to +85°C)
DESCRIPTION:
The IDT72105/72115/72125s are very high-speed, low-
power,dedicated, parallel-to-serial FIFOs. These FIFOs
possess a 16-bit parallel input port and a serial output port with
256, 512 and 1,024 word depths, respectively.
The ability to buffer wide word widths (x16) make these
FIFOs ideal for laser printers, FAX machines, local area
networks (LANs), video storage and disk/tape controller ap-
plications.
Expansion in width and depth can be achieved using
multiple chips. IDT’s unique serial expansion logic makes this
possible using a minimum of pins.
The unique serial output port is driven by one data pin (SO)
and one clock pin (SOCP). The Least Significant or Most
Significant Bit can be read first by programming the DIR pin
after a reset.
Monitoring the FIFO is eased by the availability of four
status flags: Empty, Full, Half-Full and Almost-Empty/Almost-
Full. The Full and Empty flags prevent any FIFO data overflow
or underflow conditions. The Half-Full Flag is available in both
single and expansion mode configurations. The Almost-
Empty/Almost-Full Flag is available only in a single device
mode.
The IDT72105/72115/72125 are fabricated using IDT’s
leading edge, submicron CMOS technology. Military grade
product is manufactured in compliance with the latest revision
of Mil-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
D
0–15
16
RESET
LOGIC
WRITE
POINTER
RAM
ARRAY
256 x 16
512 x 16
1,024 x 16
READ
POINTER
RSIX
RSOX
/DIR
SERIAL OUTPUT
LOGIC
EXPANSION
LOGIC
FLAG
LOGIC
SOCP
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
SO
2665 drw 01
INDUSTRIAL TEMPERATURE RANGE
©1999 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1999
DSC-2665/-
1
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
2
3
4
5
6
7
8
9
10
11
12
Vcc
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
SO
SOCP
RSOX/
/DIR
2665 drw 02
RSIX
GND
13
14
PLASTIC THIN DIP (P28-2, order code: TP)
SOIC (SO28-3, order code: SO)
TOP VIEW
PIN DESCRIPTIONS
Symbol
D
0
–D
15
Name
Inputs
Reset
I/O
I
I
Data inputs for 16-bit wide data.
When
RS
is set low, internal READ and WRITE pointers are set to the first location of the RAM
array.
FF
and
HF
go HIGH.
EF
and
AEF
go LOW. A reset is required before an initial WRITE
after power-up.
W
must be high during the
RS
cycle. Also the First Load pin (
FL
) is programmed
only during Reset.
A write cycle is initiated on the falling edge of WRITE if the Full Flag (
FF
) is not set. Data set-up
and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the
RAM array sequentially and independently of any ongoing read operation.
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (
EF
) is not set. In
both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
This is a dual purpose input used in the width and depth expansion configurations. The First
Load (
FL
) function is programmed only during Reset (
RS
) and a LOW on
FL
indicates the first
device to be loaded with a byte of data. All other devices should be programmed HIGH. The
Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the
Least Significant or Most Significant bit first.
In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain
expansion, RSIX is connected to RSOX (expansion out) of the previous device.
Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending
on the Direction pin programming. During Expansion the SO pins are tied together.
When
FF
goes LOW, the device is full and further WRITE operations are inhibited. When
HIGH, the device is not full.
When
EF
goes LOW, the device is empty and further READ operations are inhibited. When
HIGH, the device is not empty.
When
HF
is LOW, the device is more than half-full. When
half-full.
Description
RS
W
SOCP
Write
I
Serial Output
Clock
First Load/
Direction
I
I
FL
/DIR
RSIX
SO
Read Serial In
Expansion
Serial Output
Full Flag
Empty Flag
Half-Full Flag
Read Serial
Out Expansion
Almost-Empty,
Almost-Full
Flag
Power Supply
Ground
I
O
O
O
O
O
FF
EF
HF
RSOX/
AEF
FF
is
EF
is
HF
is HIGH, the device is empty to
This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an
AEF
output pin. When
AEF
is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When
AEF
is HIGH, the device is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX
connected to RSIX of the next device) a pulse is sent from RSOX to RSIX to coordinate the
width, depth or daisy chain expansion.
Single power supply of 5V.
Single ground of 0V.
2665 tbl 01
V
CC
GND
2
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
STATUS FLAGS
Number of Words in FIFO
IDT72105
0
1–31
32–128
129–224
225–255
256
IDT72115
0
1–63
64–256
257–448
449–511
512
IDT72125
0
1–127
128–512
513–896
897–1023
1024
FF
H
H
H
H
H
L
AEF
L
L
H
H
L
L
HF
H
H
H
L
L
L
EF
L
H
H
H
H
H
2665 tbl 02
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to GND
Storage Temperature
DC Output Current
(1)
RECOMMENDED DC OPERATING
CONDITIONS
Unit
V
°C
mA
Symbol
V
CC
GND
V
IH
V
IL
(1)
T
A
Parameter
Supply Voltage
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Operating Temperature
Min.
4.5
0
2.0
—
-40
Typ.
5.0
0
—
—
—
Max.
5.5
0
—
0.8
+85
Unit
V
V
V
V
°C
2665 tbl 04
Commercial
–0.5 to +7.0
–55 to +125
–50 to +50
NOTE:
2665 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 5.0V
±
10%, T
A
= -40°C to +85°C)
IDT72105
IDT72115
IDT72125
Industrial
Typ.
—
—
—
—
50
4
1
Symbol
I
LI
(1)
I
LO
(2)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic "1" Voltage I
OUT
= –2mA
(3)
Output Logic "0" Voltage I
OUT
= 8mA
(4)
Active Power Supply Current
Standby Current
(
W
=
RS
=
FL
/DIR = VIH; SOCP = VIL)
Power Down Current
Min.
–1
–10
2.4
—
—
—
—
Max.
1
10
—
0.4
100
8
6
Unit
µA
µA
V
V
mA
mA
mA
2665 tbl 05
V
OH
V
OL
I
CC1
(5)
I
CC2
(5,6,7)
I
CC3
(5,6,7)
NOTES:
1. Measurements with 0.4V
≤
V
IN
≤
V
CC.
2. SOCP = V
IL
, 0.4
≤
V
OUT
≤
V
CC
.
3. For SO, I
OUT
= –4mA.
4. For SO, I
OUT
= 16mA.
5. Tested with outputs open (I
OUT
= 0).
6.
RS
=
FL
/DIR =
W
= V
CC
- 0.2V; SOCP = 0.2V; all other inputs = V
CC
- 0.2.
7. Measurements are made after reset.
3
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 5V±10%, T
A
= -40°C to +85°C)
INDUSTRIAL
72105L25
72115L25
72125L25
Min.
Max.
—
—
35
25
10
12
0
—
—
—
25
20
8
—
3
3
—
—
—
35
35
25
25
10
7
0
10
5
—
—
5
10
28.5
50
—
—
—
—
—
35
35
35
—
—
—
14
14
14
35
35
35
—
—
—
—
—
—
—
—
—
15
15
—
—
72105L50
72115L50
72125L50
Min.
Max.
—
—
65
50
15
15
2
—
—
—
50
25
10
—
3
3
—
—
—
65
65
50
50
15
8
2
12
5
—
—
8
15
15
40
—
—
—
—
—
45
45
45
—
—
—
15
15
15
45
45
45
—
—
—
—
—
—
—
—
—
17
17
—
—
Symbol
t
S
t
SOCP
t
WC
t
WPW
t
WR
t
DS
t
DH
t
WEF
t
WFF
t
WF
t
WPF
t
SOCP
t
SOCW
t
SOPD
t
SOHZ
t
SOLZ
t
SOCEF
t
SOCFF
t
SOCF
t
REFSO
t
RSC
t
RS
t
RSS
t
RSR
t
FLS
t
FLH
t
DIRS
t
DIRH
t
SOXD1
t
SOXD2
t
SIXS
t
SIXPW
Parameter
Parallel Shift Frequency
Serial Shift Frequency
Write Cycle Time
Write Pulse Width
Write Recovery Time
Data Set-up Time
Data Hold Time
Write High to
EF
HIGH
Write Low to
FF
LOW
Write Low to Transitioning
HF
,
AEF
Write Pulse Width After
FF
HIGH
Serial Clock Cycle Time
Serial Clock Width HIGH/LOW
SOCP Rising Edge to SO Valid Data
SOCP Rising Edge to SO at High-Z
(1)
SOCP Rising Edge to SO at Low-Z
(1)
SOCP Rising Edge to
EF
LOW
SOCP Rising Edge to
FF
HIGH
SOCP Rising Edge to Transitioning
HF
,
AEF
SOCP Delay After
EF
HIGH
Reset Cycle Time
Reset Pulse Width
Reset Set-up Time
Reset Recovery Time
Figure
—
—
2
2
2
2
2
5, 6
4, 7
8
7
3
3
3
3
3
5, 6
4, 7
8
6
1
1
1
1
9
9
9
9
9
9
9
9
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2665 tbl 06
PARALLEL INPUT TIMINGS
SERIAL OUTPUT TIMINGS
RESET TIMINGS
EXPANSION MODE TIMINGS
FL
Set-up Time to
RS
Rising Edge
FL
Hold Time to
RS
Rising Edge
DIR Set-up Time to SOCP Rising Edge
DIR Hold Time from SOCP Rising Edge
SOCP Rising Edge to RSOX Rising
Edge
SOCP Rising Edge to RSOX Falling
Edge
RSIX Set-up Time to SOCP Rising
Edge
RSIX Pulse Width
NOTE:
1. Values guaranteed by design.
4
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
INDUSTRIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure A
2665 tbl 07
5V
1.1KΩ
TO
OUTPUT
PIN
680Ω
30pF
*
2665 drw 03
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
NOTE:
Parameter
(1)
Input Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
2665 tbl 08
or equivalent circuit
Figure A. Output Load
*Includes jig and scope capacitances.
1. Characterized values, not currently tested.
FUNCTIONAL DESCRIPTION
Parallel Data Input
The device must be reset before beginning operation so
that all flags are set to their initial state. In width or depth
expansion the First Load pin (
FL
) must be programmed to
indicate the first device.
The data is written into the FIFO in parallel through the D
0–
15
input data lines. A write cycle is initiated on the falling edge
of the Write (
W
) signal provided the Full Flag (
FF
) is not
asserted. If the
W
signal changes from HIGH-to-LOW and the
Full Flag (
FF
) is already set, the write line is internally inhibited
internally from incrementing the write pointer and no write
operation occurs.
Data set-up and hold times must be met with respect to the
rising edge of Write. On the rising edge of
W
, the write pointer
is incremented. Write operations can occur simultaneously or
asynchronously with read operations.
Serial Data Output
The serial data is output on the SO pin. The data is clocked
out on the rising edge of SOCP providing the Empty Flag (
EF
)
is not asserted. If the Empty Flag is asserted then the next data
word is inhibited from moving to the output register and being
clocked out by SOCP.
The serial word is shifted out Least Significant Bit or Most
Significant Bit first, depending on the
FL
/DIR level during
operation. A LOW on DIR will cause the Least Significant Bit
to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.
t
RSC
t
RS
t
RSS
t
RSR
t
RSC
,
t
RSC
,
t
RSS
SOCP
NOTE 2
t
FLS
/DIR
2665 drw 04
FLAG
STABLE
FLAG
STABLE
t
RSR
t
FLH
NOTES:
1.
EF
,
FF
,
HF
and
AEF
may change status during Reset, but flags will be valid at t
RSC.
2. SOCP should be in the steady LOW or HIGH during t
RSS
. The first LOW-HIGH (or HIGH-LOW) transition can begin after t
RSR
.
Figure 1. Reset
5
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