PCMCIA Flash Memory Card
FLV Series
PCMCIA Flash Memory Card
General Description
1 MEGABYTE through 40 MEGABYTE (Intel/Sharp based)
Features
•
Low cost High Density Linear Flash Card
•
Supports 3V or 5V only systems
•
x8/ x16 Data Interface
•Based
on Intel/Sharp FlashFile Components
•Fast
Read Performance
- 150ns @ 5V
- 200ns @ 3.3V
•
High Performance Random Writes
- 8µs Typical Word Write Time @ 5V
- 17µs Typical Word Write Time @ 3.3V
•
Automated Write and Erase Algorithms
- Command User Interface
•
100,000 Erase Cycles per Block
•
64K word symmetrical Block Architecture
•
PC Card Standard Type I Form Factor
WEDC’s FLV Series Flash memory cards offer high density
linear Flash solid state storage solutions for code and data
storage, high performance disk emulation and execute in
place (XIP) applications in mobile PC and dedicated
(embedded) equipment.
FLV series cards conform to the PCMCIA international
standard
The card’s control logic provides the system interface and
controls the internal Flash memories. The card can be
read/written in byte-wide or word-wide mode which allows
for flexible integration into various systems. Combined with
file management software, such as Flash Translation Layer
(FTL), FLV Flash cards provide removable high-
performance disk emulation.
The FLV series offers low power modes controlled by
registers. Cards contain separate 2kB EEPROM memory for
Card Information Structure (CIS) which can be used for easy
identification of card characteristics.
The WEDC FLV series is based on Intel/Sharp Flash
memories.
Note: Standard options include attribute memory. Cards
without attribute memory are available. Cards are also
available with or without a hardware write protect switch.
Architecture Overview
WEDC’s FLV series is designed to support from 2 to 20 of 4Mb, 8Mb or 16MB components, providing a wide
range of density options. Cards are based on the 28F004SC (4Mb), 28F008SC (8Mb) and 28F016SC (16Mb)
devices for 3.3V or 5V only applications. Devices codes for the 28F004SC, 28F008SC and the 28F016SC are: A7H,
A6H and AAH respectively. Systems should be able to recognize all three codes. Cards utilizing the 8Mb
components provide densities ranging from 2MB to 20MB in 2MB increments, cards utilizing 16Mb components
provide densities ranging from 4MB to 40MB in 4MB increments. 4 Mbit memory devices are used only for
smallest capacity cards (1MB).
In support of the PC Card 95 standard for word wide access, devices are paired. Therefore, the Flash array is
structured in 64K word (128kBytes) blocks. Write, read and block erase operations can be performed as either a
word or byte wide operation . By multiplexing A0, CE1# and CE2#, 8-bit hosts can access all data on data lines
DQ0 - DQ7.
The FLA21-FLA28 series also supports the following PCMCIA compatible register functions: Soft Reset via the
Configuration Option Register, Power Down (sleep mode) via the Configuration and Status Register and
monitoring of Ready/Busy, Soft Reset and Power Down via the Card Status Register (cards without attribute
memory do not have registers).
The FLV series cards conform to the PC Card (PCMCIA) and JEIDA standards, providing electrical and physical
compatibility. The PC Card form factor offers an industry standard pinout and mechanical outline, allowing density
upgrades without system design changes.
WEDC’s standard cards are shipped with WEDC’s Logo. Cards are also available with blank housings (no Logo).
The blank housings are available in both a recessed (for label) and flat housing. Please contact your WEDC sales
representative for further information on Custom artwork.
PC Card Products
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July 28, 1999
1
FLV Series
Block Diagram
Device Pair (N/2 - 1)
Device (N-1)
Device (N-2)
CSn
Device type Manuf ID Device ID
28F004SC
89
H
A7
H
28F008SC
28F016SC
89
H
89
H
A6
H
AA
H
Array
Address
Bus
ADDRESS
BUFFER
ADDRESS BUS
A1-A25
M Res
WL#
RL#
WH#
RH#
CSn
Device 3
Device 2
CS1 CS0
Control Logic
PCMCIA Interface
Cn
C0
Ctrl
At/Reg enable
Control
Address
Bus
WE#
OE#
CE2#
CE1#
REG#
A0
WP
Device Pair 1
Device Pair 0
Device 1
Device 0
CS0
4000h
SR Clr
Reg Clr
/SR
/PD
Card
Management
Registers
attrib. mem
CIS
EEPROM 2kB
Vcc
Vcc
WH# RH#
DATA
BUS
Q8-Q15
DATA
BUS
Q0-Q7
WL# RL#
0000h
control
Q0-Q7
Vcc
I/O buffer
DATA
BUS
D8-D15
DATA
BUS
D0-D7
Registers in Attribute memory space
ADDRESS
4100h
Register NAME
Status Reg.
CSR
Configuration Status Register: ADRS=4002h
not supported
Write Only
PDwn not supported
D7 D6 D5 D4
D3
D2
D1 D0
D2
Power Down; active High
1=Place all memory devices in power down mode
0=normal operation
Power On default=0
4002h
4000h
Config. and Status Reg.
Configuration Option Register
SR
Status Register: ADRS=4100h
Read Only
not supported SReset
PDwn not supported R/BSY
COR
Configuration Option Register: ADRS=4000h
-Configuration Index-
D7
D6
D5 D4 D3 D2 D1 D0
D7
Soft Reset, active High
1 = Reset State
0 = End Reset State
D6
LevelReq (not supported)
D5-D0
Configuration index (not supported)
SRES LREQ
Write Only
D7 D6
Represents the state
D2
SRESET bit in COR (4000h)
D5
D4
D3
D5
of
D1
D0
1=Reset
0=Normal operation
Power On default D5=0
D3
Represents the state of Power Down bit (D2) in CSR (4002h)
1=Power Down
D0
Reflects the card's Ready/Busy signal (pin 16) driven
by memory components Ready/Busy outputs.This bit allows
software polling of the card's Ready/Busy status.
1=Ready
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2
FLV Series
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal name
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
RDY/BSY#
Vcc
Vpp1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
WP
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal name
GND
CD1#
DQ11
DQ12
DQ13
DQ14
DQ15
CE2#
VS1
RFU
RFU
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
VS2
RST
Wait#
RFU
REG#
BVD2
BVD1
DQ8
DQ9
DQ10
CD2#
GND
I/O
O
I/O
I/O
I/O
I/O
I
I
O
Function
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Reserved
Reserved
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
Extended Bus cycle
Reserved
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
Data bit 9
Data bit 10
Card Detect 2
Ground
Active
LOW
LOW
LOW
LOW
LOW
LOW
LOW
N.C.
I
I
I
I
I
2MB(3)
4MB(3)
N.C.
8MB(3)
16MB(3)
32MB(3)
64MB(3)
N.C.
HIGH
Low(2,)
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
I
I
I
I
O
I
O
I
O
O
I/O
I/O
O
O
(2)
(2)
HIGH
LOW
Notes:
1) RDY/BSY signal is an “Open drain” type output, pull-up resistor on host side is required
2) Wait#, BVD1 and BVD2 are driven high for compatibility
3) Shows density for which specified address bit is MSB. Higher order address bits are no connects (ie 4MB A21 is MSB A22 - A25 are NC).
Mechanical
1.0mm
±
0.05
(0.039”)
Interconnect area
1.6mm
±
0.05
(0.063”)
10.0mm MIN
(0.400”)
3.0mm MIN
Substrate area
54.0mm
±
0.10
(2.126”)
1.0mm
±
0.05
(0.039”)
10.0mm MIN
(0.400”)
85.6mm
±
0.20
(3.370”)
3.3mm
±
T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
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July 28, 1999
3
FLV Series
Card Signal Description
Symbol
Type
INPUT
A0 - A25
DQ0 - DQ15
CE1#, CE2#
OE#
WE#
RDY/BSY#
INPUT/OUTPUT
INPUT
INPUT
INPUT
OUTPUT
CD1#, CD2#
WP
OUTPUT
OUTPUT
VPP1, VPP2
VCC
GND
REG#
RST
WAIT#
BVD1, BVD2
VS1, VS2
RFU
N.C.
N.C.
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
Name and Function
ADDRESS INPUTS:
A0 through A25 enable direct addressing of up to
64MB of memory on the card. Signal A0 is not used in word access mode.
A25 is the most significant bit
DATA INPUT/OUTPUT:
DQ0 THROUGH DQ15 constitute the bi-
directional databus. DQ15 is the MSB.
CARD ENABLE 1 AND 2:
CE1# enables even byte accesses, CE2#
enables odd byte accesses. Multiplexing A0, CE1# and CE2# allows 8-bit
hosts to access all data on DQ0 - DQ7.
OUTPUT ENABLE:
Active low signal gating read data from the memory
card.
WRITE ENABLE:
Active low signal gating write data to the memory card.
READY/BUSY OUTPUT:
Indicates status of internally timed erase or
program algorithms. A high output indicates that the card is ready to
accept accesses. A low output indicates that one or more devices in the
memory card are busy with internally timed erase or write activities.
CARD DETECT 1 and 2:
Provide card insertion detection. These signals
are internally connected to ground on the card. The host shall monitor
these signals to detect card insertion (pulled-up on host side).
WRITE PROTECT:
Write protect reflects the status of the Write Protect
switch on the memory card. WP set to high = write protected, providing
internal hardware write lockout to the Flash array.
If card does not include optional write protect switch, this signal will be
pulled low internally indicating write protect = "off".
PROGRAM/ERASE POWER SUPPLY:
Provides programming voltages
for card . Not connected for 3.3V/5V only card.
CARD POWER SUPPLY:
(3.3V or 5.0V nominal).
CARD GROUND
ATTRIBUTE MEMORY SELECT :
Active low signal, enables access to
Attribute Memory Plane, occupied by Card Information Structure and Card
Registers.
RESET:
Active high signal for placing card in Power-on default state.
Reset can be used as a Power-Down signal for the memory array.
WAIT:
This signal is pulled high internally for compatibility. No wait states
are generated.
BATTERY VOLTAGE DETECT:
These signals are pulled high to
maintain SRAM card compatibility.
VOLTAGE SENSE:
Notifies the host socket of the card's VCC
requirements. VS1 grounded and VS2 are open to indicate a 3.3V/5V card.
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD:
pin may be driven or left
floating
Functional Truth Table
READ function
Common Memory
Attribute Memory
Function Mode
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
WRITE function
/CE2 /CE1
H
H
H
L
H
L
L
L
L
H
H
H
H
L
L
H
L
L
L
H
A0
X
L
H
X
X
X
L
H
X
X
/OE
X
L
L
L
L
X
H
H
H
H
/WE
X
H
H
H
H
X
L
L
L
L
/REG D15-D8
D7-D0
X
High-Z
High-Z
H
High-Z Even-Byte
H
High-Z
Odd-Byte
H
Odd-Byte Even-Byte
H
Odd-Byte
High-Z
X
H
H
H
H
X
X
X
Even-Byte
X
Odd-Byte
Odd-Byte Even-Byte
Odd-Byte
X
/REG D15-D8
D7-D0
X
High-Z
High-Z
L
High-Z Even-Byte
L
High-Z Not Valid
L Not Valid Even-Byte
L Not Valid
High-Z
X
L
L
L
L
X
X
X
X
X
X
Even-Byte
X
Even-Byte
X
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
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July 28, 1999
4
FLV Series
Absolute Maximum Ratings (1)
Operating Temperature TA (ambient)
Commercial
Industrial
Storage Temperature
Commercial
Industrial
Voltage on any pin relative to VSS
VCC supply Voltage relative to VSS
DC Characteristics
(1)
Symbol Parameter
I
CCR
I
CCW
I
CCE
I
CCS
(CMOS)
VCC Read Current
VCC Program Current
VCC Erase Current
VCC Standby Current
Notes:
(1) Stress greater than those listed under “Absolute
Maximum ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation at these or any other conditions
greater than those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
0°C to +60 °C
-40°C to +85 °C
-30°C to +80 °C
-40°C to +85 °C
-0.5V to VCC+0.5V
-0.5V to +7.0V
Vcc = 3.3V / 5V
Density
(Mbytes)
All
All
All
2MB
20MB
4MB
40MB
2
28F008SC
Notes
28F008SC
28F016SC
3.3V Vcc
5V Vcc
Units Test Conditions
Typ
(3)
Max Typ
(3)
Max
10
12
20
35
mA VCC = VCCmax
tcycle = 150ns,CMOS levels
60
75
mA
40
50
400
50
400
200
200
60
420
60
420
230
50
230
mA
µA
VCC = VCCmax
Control Signals = VCC
Reset = VSS, CMOS levels
2
28F016SC
CMOS Test Conditions: VCC = 5V ± 5%, VIL = VSS ± 0.2V, VIH = VCC ± 0.2V
Notes:
1. All currents are RMS values unless otherwise specified. ICCR, ICCW and ICCE are based on Byte wide operations. For 16 bit
operation values are double.
2. Control Signals: CE
1
#, CE
2
#, OE#, WE#, REG#
3. Typical: VCC = 5V, T = +25C
Symbol
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
V
LKO
Parameter
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VCC Erase/Program
Lock Voltage
Notes
1
1
1
1
1
1
1
Min
Max
±20
±20
Units
µA
µA
V
V
V
V
V
Test Conditions
VCC = VCCMAX
Vin =VCC or VSS
VCC = VCCMAX
Vout =VCC or VSS
0
0.7VCC
VCC-0.4
2.0
0.8
VCC+0.5
0.4
VCC
IOL = 3.2mA
IOH = -2.0mA
Notes:
1) Values are the same for byte and word wide modes for all card densities.
2) Exceptions: Leakage currents on CE1#, CE2#, OE#, REG# and WE# will be < 500 µA when VIN = GND due to
internal pull-up resistors. Leakage currents on RST will be <150µA when VIN=VCC due to internal pull-down resistor
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July 28, 1999
5
FLV Series
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