xr
NOVEMBER 2005
XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
REV. 2.1.3
GENERAL DESCRIPTION
The XR16C2850
1
(2850) is an enhanced dual
universal asynchronous receiver and transmitter
(UART). Enhanced features include 128 bytes of TX
and RX FIFOs, programmable TX and RX FIFO
trigger level, FIFO level counters, automatic (RTS/
CTS) hardware and (Xon/Xoff) software flow control,
automatic RS-485 half duplex direction control output
and data rates up to 6.25 Mbps at 5V and 8X
sampling clock.
Onboard status registers provide the user
with operational status and data error flags. An internal
loopback capability allows system diagnostics.
The 2850
has a full modem interface and can operate at 2.97V
to 5.5V and is pin-to-pin compatible to Exar’s
ST16C2550 and XR16C2750 except the 48-TQFP
package. The 2850 register set is compatible to the
industry standard ST16C2550 and is available in 48-
pin TQFP and 44-pin PLCC packages.
N
OTE
:
1 Covered by U.S. Patent #5,649,122 and #5,949,787
FEATURES
Added feature in devices with a top mark date code of
"F2 YYWW" and newer:
■
■
5V tolerant inputs
0 ns address hold time (T
AH
)
•
Pin-to-pin compatible and functionally compatible to
Exar’s ST16C2550 and XR16L2750 and TI’s
TL16C752B in the 48-TQFP package
•
Pin-alike Exar’s XR16L2750 and ST16C2550 48-
TQFP package but with additional CLK8/16,
CLKSEL and HDCNTL inputs
•
Two independent UART channels
■
■
■
■
■
■
■
■
■
■
■
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
Register set compatible to 16C550
Up to 6.25 Mbps at 5V, and 4 Mbps at 3.3V
Transmit and Receive FIFOs of 128 bytes
Programmable TX and RX FIFO Trigger Levels
Transmit and Receive FIFO Level Counters
Automatic Hardware (RTS/CTS) Flow Control
Selectable Auto RTS Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Auto RS-485 Half-duplex Direction Control
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Full modem interface
•
Device Identification and Revision
•
Crystal oscillator or external clock input
•
Industrial and commercial temperature ranges
•
48-TQFP and 44-PLCC packages
F
IGURE
1. XR16C2850 B
LOCK
D
IAGRAM
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
HDCNTL#
CLKSEL
CLK8/16
Reset
8-bit Data
Bus
Interface
UART Channel A
UART
Regs
BRG
128 Byte TX FIFO
TX & RX
IR
ENDEC
2.97V to 5.5V VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
128 Byte RX FIFO
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
xr
REV. 2.1.3
TXRDYA#
48
VCC
45
43
42
41
40
38
47
46
44
39
37
HDCNTL#
DSRA#
RIA#
D2
D1
D0
CTSA#
D4
D3
CDA#
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
1
2
3
4
5
6
7
8
9
36
35
34
33
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
CLKSEL
XR16C2850
48-pin TQFP
32
31
30
29
28
27
26
25
CSA# 10
CSB# 11
NC 12
15
13
18
19
20
22
16
14
17
21
23
CTSB#
24
CLK8/16
GND
DSRB#
RXRDYB#
RTSB#
CDB#
XTAL2
IOW#
XTAL1
IOR#
RIB#
TXRDYA#
DSRA#
41
44
43
42
40
6
5
4
3
2
1
CTSA#
CDA#
RIA#
VCC
D4
D3
D2
D1
D0
D5
D6
D7
RXB
RXA
7
8
9
10
11
39
38
37
36
RESET
DTRB#
DTRA#
RTSA#
TXRDYB# 12
TXA
TXB
13
14
XR16C2850
44-pin PLCC
35 OP2A#
34
33
32
31
RXRDYA#
INTA
INTB
A0
OP2B# 15
CSA# 16
CSB# 17
XTAL1 18
XTAL2 19
IOW# 20
CDB# 21
GND 22
RXRDYB# 23
IOR# 24
DSRB# 25
RIB# 26
RTSB# 27
CTSB# 28
30 A1
29
A2
ORDERING INFORMATION
O
PERATING
P
ART
N
UMBER
XR16C2850CJ
XR16C2850CM
XR16C2850IJ
XR16C2850IM
P
ACKAGE
44-Lead PLCC
48-Lead TQFP
44-Lead PLCC
48-Lead TQFP
T
EMPERATURE
R
ANGE
0°C to +70°C
0°C to +70°C
Active
Active
D
EVICE
S
TATUS
-40°C to +85°C Active
-40°C to +85°C Active
2
xr
REV. 2.1.3
XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
PIN DESCRIPTIONS
N
AME
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
29
30
31
9
8
7
6
5
4
3
2
24
26
27
28
3
2
1
48
47
46
45
44
19
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
UART channel A Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output is LOW when MCR[3] is set to a logic 1. INTA
is set to the three state mode and OP2A# is HIGH when MCR[3] is set
to a logic 0 (default). See MCR[3]. If this output is not used, leave it
unconnected.
UART channel B Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output is LOW when MCR[3] is set to a logic 1. INTB
is set to the three state mode and OP2B# is HIGH when MCR[3] is set
to a logic 0 (default). See MCR[3]. If this output is not used, leave it
unconnected.
IOW#
20
15
I
CSA#
CSB#
INTA
16
17
33
10
11
30
I
I
O
INTB
32
29
O
TXRDYA#
1
43
O
UART channel A Transmitter Ready (active low). The output
provides the TX FIFO/THR status for transmit channel A. See
Table 2.
If this output is not used, leave it unconnected.
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
Table 2
. If this output
is not used, leave it unconnected.
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
Table 2
. If this
output is not used, leave it unconnected.
RXRDYA#
34
31
O
TXRDYB#
12
6
O
3
XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
N
AME
RXRDYB#
44-PLCC
P
IN
#
23
48-TQFP
P
IN
#
18
T
YPE
O
D
ESCRIPTION
xr
REV. 2.1.3
UART channel B Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel B. See
Table 2
. If this output
is not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
13
7
O
UART channel A Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface isLOW. If this output is not used, leave it uncon-
nected.
UART channel A Receive Data or infrared receive data. Normal receive
data input must idle HIGH. The infrared receiver pulses typically idles
LOW but can be inverted by software control prior going in to the
decoder, see MCR[6] and FCTR[2]. If this pin is not used, tie it to VCC
or pull it high via a 100k ohm resistor.
UART channel A Request-to-Send (active low) or general purpose out-
put. This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto
RS485 half-duplex direction control, see FCTR[3]. If this output is not
used, leave it unconnected.
UART channel A Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
UART channel A Data-Terminal-Ready (active low) or general purpose
output. If this output is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used.
UART channel A Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used.
UART channel A Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used.
Output Port 2 Channel A - The output state is defined by the user and
through the software setting of MCR[3]. INTA is set to the active mode
and OP2A# output is LOW when MCR[3] is set to a logic 1. INTA is set
to the three state mode and OP2A# is HIGH when MCR[3] is set to a
logic 0. See MCR[3]. This output can only be used as a general pur-
pose output when interrupts are not used, otherwise it will disturb the
INTA output functionality. If this output is not used, leave it uncon-
nected.
UART channel B Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If this output is not used, leave it uncon-
nected.
RXA
11
5
I
RTSA#
36
33
O
CTSA#
40
38
I
DTRA#
DSRA#
CDA#
RIA#
OP2A#
37
41
42
43
35
34
39
40
41
32
O
I
I
I
O
TXB
14
8
O
4
xr
REV. 2.1.3
XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
48-TQFP
P
IN
#
4
T
YPE
I
D
ESCRIPTION
UART channel B Receive Data or infrared receive data. Normal receive
data input must idle HIGH. The infrared receiver pulses typically idles
LOW but can be inverted by software control prior going in to the
decoder, see MCR[6] and FCTR[2]. If this pin is not used, tie it to VCC
or pull it high via a 100k ohm resistor.
UART channel B Request-to-Send (active low) or general purpose out-
put. This port must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto
RS485 half-duplex direction control, see FCTR[3] and EMSR[3]. If this
output is not used, leave it unconnected.
UART channel B Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
UART channel B Data-Terminal-Ready (active low) or general purpose
output. If this output is not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output is LOW when MCR[3] is set to a logic 1. INTB is set
to the three state mode and OP2B# is HIGH when MCR[3] is set to a
logic 0. See MCR[3]. This output can only be used as a general pur-
pose output when interrupts are not used, otherwise it will disturb the
INTB output functionality. If this output is not used, leave it uncon-
nected.
N
AME
RXB
44-PLCC
P
IN
#
10
RTSB#
27
22
O
CTSB#
28
23
I
DTRB#
DSRB#
38
25
35
20
O
I
CDB#
21
16
I
RIB#
26
21
I
OP2B#
15
9
O
ANCILLARY SIGNALS
XTAL1
XTAL2
HDCNTL#
18
19
-
13
14
37
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
RS-485 half duplex directional control for channel A and B (active low).
Connect to VCC for normal RTS# function and connect to GND for RS-
485 half duplex direction control. RTS# pin goes LOW for transmit and
HIGH for receive during RS-485 mode. This pin is wire “OR-ed” with
FCTR[3]. If this pin is connected to VCC, the function of the RTS# pin
can be controlled via FCTR[3]. If this pin is connected to GND, the
RTS# pin will always be the RS-485 half duplex direction control and
can not be controlled via FCTR[3]. See FCTR[3].
5
PCB Design
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