M48Z08
M48Z18
5V, 64 Kbit (8Kb x 8) ZEROPOWER
®
SRAM
FEATURES SUMMARY
■
■
■
■
■
■
■
■
INTEGRATED, ULTRA LOW POWER SRAM
AND POWER-FAIL CONTROL CIRCUIT
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48Z08: V
CC
= 4.75 to 5.5V
4.5V
≤
V
PFD
≤
4.75V
– M48Z18: V
CC
= 4.5 to 5.5V
4.2V
≤
V
PFD
≤
4.5V
SELF-CONTAINED BATTERY IN THE
CAPHAT™ DIP PACKAGE
PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 8K x 8 SRAMs
RoHS COMPLIANCE
Lead-free components are compliant with the
RoHS Directive.
Figure 1. 28-pin CAPHAT, DIP Package
28
1
PCDIP28 (PC)
Battery CAPHAT™
Rev 5.0
December 2005
1/16
M48Z08, M48Z18
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 28-pin CAPHAT, DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2.
Table 1.
Figure 3.
Figure 4.
Logic Diagram . .
Signal Names . .
DIP Connections
Block Diagram . .
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......
......
.....3
.....3
.....3
.....4
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. AC Testing Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . . 13
Table 11. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . . 13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
M48Z08, M48Z18
SUMMARY DESCRIPTION
The M48Z08/18 ZEROPOWER
®
RAM is a 8K x 8
non-volatile static RAM which is pin and functional
compatible with the DS1225.
The monolithic chip is available in two special
packages to provide a highly integrated battery
backed-up memory solution.
The M48Z08/18 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
Figure 2. Logic Diagram
VCC
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the
M48Z08/18 silicon with a long life lithium button
cell in a single package.
Table 1. Signal Names
A0-A12
DQ0-DQ7
Address Inputs
Data Inputs / Outputs
Chip Enable
Output Enable
WRITE Enable
Supply Voltage
Ground
Not Connected Internally
13
A0-A12
M48Z08
M48Z18
8
DQ0-DQ7
E
G
W
E
G
W
V
CC
V
SS
NC
VSS
AI01022
Figure 3. DIP Connections
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
M48Z08 22
M48Z18 21
8
9
20
10
19
11
18
12
17
13
16
14
15
AI01183
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
3/16
M48Z08, M48Z18
Figure 4. Block Diagram
A0-A12
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
POWER
8K x 8
SRAM ARRAY
DQ0-DQ7
VPFD
E
W
G
VCC
VSS
AI01394
OPERATION MODES
The M48Z08/18 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When V
CC
is out of tolerance, the circuit write
protects the SRAM, providing a high degree of
Table 2. Operating Modes
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
V
SO
to V
PFD
(min)
(1)
≤
V
SO(1)
4.75 to 5.5V
or
4.5 to 5.5V
V
CC
E
V
IH
V
IL
V
IL
V
IL
X
X
G
X
X
V
IL
V
IH
X
X
W
X
V
IL
V
IH
V
IH
X
X
DQ0-DQ7
High Z
D
IN
D
OUT
High Z
High Z
High Z
Power
Standby
Active
Active
Active
CMOS Standby
Battery Back-up Mode
data security in the midst of unpredictable system
operation brought on by low V
CC
. As V
CC
falls be-
low approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
Note: X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
1. See
Table 10., page 12
for details.
4/16
M48Z08, M48Z18
READ Mode
The M48Z08/18 is in the READ Mode whenever W
(WRITE Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 65,536 locations in the
static storage array. Thus, the unique address
specified by the 13 address inputs defines which
one of the 8,192 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within address access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
Figure 5. READ Mode AC Waveforms
tAVAV
A0-A12
tAVQV
tELQV
E
tELQX
tGLQV
G
tGLQX
DQ0-DQ7
VALID
AI01385
available after the latter of the Chip Enable Access
time (t
ELQV
) or Output Enable Access time
(t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the address in-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
AXQX
) but will go indeterminate until the next
address access.
VALID
tAXQX
tEHQZ
tGHQZ
Note: WRITE Enable (W) = High.
Table 3. READ Mode AC Characteristics
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
ELQX(2)
t
GLQX(2)
t
EHQZ(2)
t
GHQZ(2)
t
AXQX
Parameter
(1)
READ Cycle Time
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
5
10
5
50
40
M48Z08/M48Z18
Unit
Min
100
100
100
50
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: 1. Valid for Ambient Operating Temperature: T
A
= 0 to 70°C; V
CC
= 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2. C
L
= 30pF.
5/16
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