Austin Semiconductor, Inc.
256K x 36 SSRAM
Flow-Through, Synchronous
Burst SRAM
FEATURES
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!
!
!
!
!
!
AS5SS256K36 &
AS5SS256K36A
PIN ASSIGNMENT
(Top View)
SSRAM
!
!
!
!
!
!
Organized 256K x 36
Fast Clock and OE\ access times
Single +3.3V +0.3V/-0.165V power supply (V
DD
)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL WRITE
Three chip enables for simple depth expansion and address
pipelining
Clock-controlled and registered addresses, data I/Os and
control signals
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Automatic power-down for portable applications
100-lead TQFP package for high density, high speed
Low capacitive bus loading
100-pin TQFP (DQ)
(2-chip enable version, “A” indicator)
SA
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
V
DD
SA
BWa\
BWb\
BWc\
BWd\
CE2
CE\
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
OPTIONS
Timing
8.5ns/10ns/100MHz
10ns/15ns/66MHz
!
Packages
100-pin TQFP (2-chip enable)
!
Pinout
2-chip Enables
3-chip Enables
!
Operating Temperature Ranges
Military (-55
o
C to +125
o
C)
Industrial (-40
o
C to +85
o
C)
!
MARKING
-8.5*
-10
DQ No. 1001
A
(PRELIMINARY)
no indicator
XT*
IT
DQPc
DQc
DQc
V
DD
Q
Vss
DQc
DQc
DQc
DQc
Vss
V
DD
Q
DQc
DQc
Vss
V
DD
NC
Vss
DQd
DQd
V
DD
Q
Vss
DQd
DQd
DQd
DQd
Vss
V
DD
Q
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
V
DD
Q
Vss
DQb
DQb
DQb
DQb
Vss
V
DD
Q
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
100-pin TQFP (DQ)
(3-chip enable version, no indicator)
SA
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
V
DD
CE2\
BWa\
BWb\
BWc\
BWd\
CE2
CE\
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
SA
SA
SA
SA
SA
SA
NF
NF
V
DD
Vss
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
*NOTE:
-8.5/XT combination not available.
GENERAL DESCRIPTION
The AS5SS256K36 employs high-speed, low-power CMOS
designs that are fabricated using an advanced CMOS process.
This 8Mb Synchronous Burst SRAM integrates a 256K x 36
SRAM core with advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK). The synchro-
nous inputs include all addresses, all data inputs, active LOW chip en-
able (CE\), two additional chip enables for easy depth expansion (CE2\,
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables
(BWx\) and global write (GW\). Note that CE2\ is not available on the
A version.
DQPc
DQc
DQc
V
DD
Q
Vss
DQc
DQc
DQc
DQc
Vss
V
DD
Q
DQc
DQc
Vss
V
DD
NC
Vss
DQd
DQd
V
DD
Q
Vss
DQd
DQd
DQd
DQd
Vss
V
DD
Q
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
V
DD
Q
Vss
DQb
DQb
DQb
DQb
Vss
V
DD
Q
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
Vss
DQa
DQa
DQa
DQa
Vss
V
DD
Q
DQa
DQa
DQPa
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS5SS256K36 &
AS5SS256K36A
Rev. 3.5 2/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SA
SA
SA
SA
SA
SA
SA
SA
NF
V
DD
Vss
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
1
Austin Semiconductor, Inc.
GENERAL DESCRIPTION (continued)
Asynchronous inputs include the output enable (OE\),
clock (CLK) and snooze enable (ZZ). There is also a burst
mode input (MODE) that selects between interleaved and lin-
ear burst modes. The data-out (Q), enabled by OE\, is also
asynchronous. WRITE cycles can be from one to four bytes
wide as controlled by the write control inputs.
Burst operation can be initiated with either address
status processor (ADSP\) or address status controller (ADSC\)
inputs. Subsequent burst addresses can be internally gener-
ated as controlled by the burst advance input (ADV\).
Address and write control are registered on-chip to
AS5SS256K36 &
AS5SS256K36A
SSRAM
simplify WRITE cycles. This allows self-timed WRITE cycles.
Individual byte enables allow individual bytes to be written.
During WRITE cycles on the x18 device, BWa\ controls DQa’s
and DQPa; BWb\ controls DQb’s and DQPb; BWc\ controls
DQc’s and DQPc; BWd\ controls DQd’s and DQPd. GW\ LOW
causes all bytes to be written. Parity bits are also featured on
this device.
This 8Mb Synchronous Burst SRAM operates from a
+3.3V V
DD
power supply, and all inputs and outputs are TTL-
compatible. The device is ideally suited for 486, Pentium
©
, 680x0
and PowerPC
TM
systems and those systems that benefit from a
wide synchronous data bus.
FUNCTIONAL BLOCK DIAGRAM
18
SA0, SA1, SAs
MODE
ADV\
CLK
ADDRESS
REGISTER
18
SA0-SA1
16
18
BINARY
COUNTER
AND LOGIC
CL
Q1
SA1'
Q0
ADSC\
ADSP\
BWd\
BYTE "d"
WRITE REGISTER
SA0'
BYTE "d"
WRITE DRIVER
BWc\
BYTE "c"
WRITE REGISTER
BYTE "c"
WRITE DRIVER
256K x 9 x 4
(x36)
DQs
BWb\
BYTE "b"
WRITE REGISTER
BYTE "b"
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
DQPa
OUTPUT
BUFFERS
DQPb
DQPc
DQPd
BWa\
BWE\
GW\
CE\
CE2
CE2\
OE\
BYTE "a"
WRITE REGISTER
ENABLE
REGISTER
BYTE "a"
WRITE DRIVER
INPUT
REGISTERS
4
NOTE:
Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions and time diagrams for detailed
information.
AS5SS256K36 &
AS5SS256K36A
Rev. 3.5 2/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
Austin Semiconductor, Inc.
PIN DESCRIPTION
AS5SS256K36 &
AS5SS256K36A
SSRAM
Pin Number
SYMBOL TYPE
DESCRIPTION
37
36
32-35, 44-50,
SA0
Synchronous Address Inputs: These inputs are registered and must
81, 82, 99,
SA1
Input meet the setup and hold times around the rising edge of CLK. Two
100
SA
different pinouts are available for the TQFP packages.
92 (A version)
43 (3 CE version)
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold times
BWa\
93
around the rising edge of CLK. A byte write enable is LOW for a WRITE
94
BWb\
Input cycle and HIGH for a READ cycle. Bwa\ controls DQa pins and DQPa;
BWc\
95
Bwb\ controls DQb pins and DQPb; Bwc\ controls DQc pins and DQPc;
96
BWd\
Bwd\ controls DQd pins and DQPd. Parity bits are featured on this
device.
Byte Write Enable: This active LOW input permits BYTE WRITE
87
BWE\
Input operations and must meet the setup and hold items around the rising
edge of CLK.
Global Write: This active LOW input allows a full 36-bit WRITE to occur
88
GW\
Input independent of the BWE\ and BWx\ lines and must meet the setup and
hold times around the rising edge of CLK.
Clock: CLK registers address, data, chip enable, byte write enables and
89
CLK
Input burst control inputs on its rising edge. All synchronous inputs must meet
setup and hold times around the clock's rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the
98
CE\
Input device and conditions the internal use of ADSP\. CE\ is sampled only
when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable the
92
CE2\
Input device and is sampled only when a new external address is loaded.
(3 CE version)
CE2\ is only available on the 3 CE version.
97
86
CE2
OE\
Input
Input
Synchronous Chip Enable: This active HIGH input is used to enable the
device and is sampled only when a new external address is loaded.
83
ADV\
85
ADSC\
Output Enable: This active LOW, asynchronous input enables the data
I/O output drivers.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on this pin effectively causes wait
Input
states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV\ must be HIGH at the rising edge of
the first clock after an ADSP\ cycle is initiated.
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
Input registered. A READ or WRITE is performed using the new address if
CE\ is LOW. ADSC\ is also used to place the chip into power-down state
when CE\ is HIGH.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS256K36 &
AS5SS256K36A
Rev. 3.5 2/03
3
Austin Semiconductor, Inc.
PIN DESCRIPTION (continued)
Pin Number
SYMBOL TYPE
AS5SS256K36 &
AS5SS256K36A
SSRAM
84
ASDP\
31
MODE
64
(a) 52, 53, 56-59,
62, 63
(b) 68, 69, 72-75,
78, 79
(c) 2, 3, 6-9, 12,
13
(d) 18, 19, 22-25,
28, 29
51
80
1
30
ZZ
DESCRIPTION
Synchronous Address Status Processor: This active LOW inputs
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address, independent of
Input
the byte write enables and ADSC\, but dependent upon CE\, CE2 and
CE2\. ADSP\ is ignored if CE\ is HIGH. Power-down state is entered if
CE2 is LOW or CE2\ is HIGH.
MODE: This inputs selects the burst sequence. A LOW on this pin
Input select "linear burst." NC or HIGH on this pin selects "interleaved burst."
Do not alter input state while device is operating.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
Input
memory array is retained. When ZZ is active, all other inputs are
ignored.
DQa
DQb
DQc
DQd
SRAM Data I/O's: Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is
Input/
DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold
Output
times around the rising edge of CLK.
NC/DQPa
NC/DQPb
Parity Data I/Os: Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte
NC/ I/O
NC/DQPc
"c" parity is DQPc; Byte "d" parity is DQPd.
NC/DQPd
Power Supply: See DC Electrical Characteristics and Operating
Supply
15, 41, 65, 91
V
DD
Conditions for range.
Isolated Output Buffer Supply: See DC Electrical Characteristics and
4, 11, 20, 27, 54,
V
DD
Q
Supply
Operating Conditions for range.
61, 70, 77
5, 10, 14, 17, 21,
26, 40, 55, 60, 67,
Vss
Supply Ground: GND
71, 76, 90
Do Not Use: These signals may either be unconnected or wired to GND
38, 39
DNU
---
to improve package heat dissipation.
No Connect: These signals are not internally connected and may be
16, 66
NC
---
connected to GND to improve package heat dissipation.
No Function: These pins are internally connected to the die and have
42
the capacitance of an input pin. It is allowable to leave these pins
NF
---
43 (A version)
unconnected or driven by signals. On the 3 CE version, pin 42 is
reserved as an address upgrade pin for the 16Mb Synchronous Burst.
AS5SS256K36 &
AS5SS256K36A
Rev. 3.5 2/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
Austin Semiconductor, Inc.
AS5SS256K36 &
AS5SS256K36A
SSRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X00
X…X11
X…X10
X…X10
X…X11
X…X00
X…X01
X…X11
X…X10
X…X01
X…X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X10
X…X11
X…X00
X…X10
X…X11
X…X00
X…X01
X…X11
X…X00
X…X01
X…X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS
FUNCTION
READ
READ
WRITE Byte "a"
WRITE All Bytes
WRITE All Bytes
GW\
H
H
H
H
L
BWE\
H
L
L
L
X
BWa\
X
H
L
L
X
BWb\
X
H
H
L
X
BWc\
X
H
H
L
X
BWd\
X
H
H
L
X
AS5SS256K36 &
AS5SS256K36A
Rev. 3.5 2/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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