D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
SN74ACT3638
512
×
32
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
D
D
D
D
D
D
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Two Independent 512
×
32 Clocked FIFOs
Buffering Data in Opposite Directions
Read Retransmit Capability From FIFO on
Port B
Mailbox-Bypass Register for Each FIFO
Programmable Almost-Full and
Almost-Empty Flags
Microprocessor Interface Control Logic
D
D
D
D
D
D
IRA, ORA, AEA, and AFA Flags
Synchronized by CLKA
IRB, ORB, AEB, and AFB Flags
Synchronized by CLKB
Low-Power 0.8-µm Advanced CMOS
Technology
Supports Clock Frequencies up to 67 MHz
Fast Access Times of 11 ns
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Quad Flat
(PQ) Packages
PCB PACKAGE
(TOP VIEW)
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
GND
A11
A10
A9
A8
A7
A6
GND
A5
A4
A3
V
CC
A2
A1
A0
GND
B0
B1
B2
B3
B4
B5
GND
B6
V
CC
Copyright
©
1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
B7
B8
B9
B10
B11
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
CSA
W/RA
ENA
CLKA
V
CC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
V
CC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
V
CC
A12
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
GND
IRA
ORA
NC
AFA
AEA
MBF2
V
CC
MBA
RSTA
V
CC
RDYA
RTM
RFM
GND
RDYB
FS0
FS1
RSTB
V
CC
MBB
MBF1
GND
AEB
GND
AFB
NC
ORB
IRB
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
CSB
W/RB
ENB
CLKB
GND
B31
B30
B29
B28
B27
B26
V
CC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
V
CC
B15
B14
B13
B12
GND
1
SN74ACT3638
512
×
32
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
PQ PACKAGE†
(TOP VIEW)
17 16 15 14 13 12 11 10 9
8
7
6
5
NC
CSB
W/RB
ENB
CLKB
GND
B31
B30
B29
B28
B27
B26
V
CC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
V
CC
B15
B14
B13
B12
GND
NC
NC
RST2
FS1
FS0
RDYB
GND
RFM
RTM
RDYA
V
CC
RST1
MBA
V
CC
MBF2
AEA
AFA
NC
ORA
IRA
GND
NC
4
3
2
126 124
122 120 118
1 132 130 128
129
121
119
131
127
125 123
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
NC
NC
V
CC
IRB
ORB
NC
AFB
GND
AEB
GND
MBF1
MBB
V
CC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
CSA
W/RA
ENA
CLKA
V
CC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
V
CC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
V
CC
A12
NC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC – No internal connection
† Uses Yamaichi socket IC51-1324-828
2
NC
B11
B10
B9
B8
B7
V
CC
B6
GND
B5
B4
B3
B2
B1
B0
GND
A0
A1
A2
V
CC
A3
A4
A5
GND
A6
A7
A8
A9
A10
A11
GND
NC
NC
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN74ACT3638
512
×
32
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
description
The SN74ACT3638 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock
frequencies up to 67 MHz and has read access times as fast as 11 ns. Two independent 512
×
32 dual-port
SRAM FIFOs on the chip buffer data in opposite directions. The FIFO memory buffering data from port A to port
B has retransmit capability, which allows previously read data to be accessed again. Each FIFO has flags to
indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when
a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via
two 32-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two
or more devices can be used in parallel to create wider datapaths.
The SN74ACT3638 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The input-ready (IRA, IRB) flags and almost-full (AFA, AFB) flags of the SN74ACT3638 are two-stage
synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flags and almost-empty
(AEA, AEB) flags of the SN74ACT3638 are two-stage synchronized to the port clock that reads data from its
array. Offsets for the almost-full and almost-empty flags of both FIFOs can be programmed from port A.
The SN74ACT3638 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the application reports
FIFO Mailbox-Bypass Registers: Using
Bypass Registers to Initialize DMA Control
(literature number SCAA007) and
Metastability Performance of
Clocked FIFOs
(literature number SCZA004).
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN74ACT3638
512
×
32
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
functional block diagram
MBF1
Mail1
Register
Port-A
Control
Logic
512
×
32
SRAM
RST1
FIFO1,
Mail1
Reset
Logic
Output Register
Input Register
CLKA
CSA
W/RA
ENA
MBA
32
Sync Retransmit
Logic
RTM
RFM
Write
Pointer
Read
Pointer
IRA
AFA
FIFO1
Status-Flag
Logic
ORB
AEB
FS0
FS1
A0 – A31
RDYA
9
Programmable-
Flag
Offset Registers
RDYB
B0 – B31
FIFO2
ORA
AEA
Status-Flag
Logic
IRB
AFB
Read
Pointer
Write
Pointer
32
Output Register
Input Register
512
×
32
SRAM
FIFO2,
Mail2
Reset
Logic
RST2
Port-B
Control
Logic
Mail2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
京公网安备 11010802033920号
EEWORLD
